#!/bin/regdecode UIO Driver for LE450 CPLD

# le-450 CPLD Register Map and Register Definitions
# Rev 0.1

# 0x0 RO Version
# 0x1 RO Board IDs
# 0x2 RO Status Inputs
# 0x3 RW Resets
# 0x4 RW Resets 2
# 0x5 RW I2C Select
# 0x6 RW Fan Enables & Dying Gasp
# 0x7 RW FPP Cfg & Status
# 0x8 RW FPP Data
# 0x9 WC Interrupt Status 0
# 0xa RW Interrupt Mask 0
# 0xb WO Interrupt Test 0
# 0xc WO Self Reset
# 0xd WO Power Cycle
# 0x0e RW LED control


[LE450CPLD_VER]
name: Version Register, 0x0
width: 8
field:	7:4	MJR	- RO Major Version #
field:	3:0	MNR	- RO Minor Version #

[LE450CPLD_BID]
name: Board ID Register, 0x1
width: 8
field:	7	-	0x0 RO Reserved
field:	6:4	MEZZ	- RO Mezz board ID
field:	3:0	MAIN	- RO Main board ID

[LE450CPLD_STS]
name: Status Register, 0x2
width: 8
field:	7	FAN_PRES	- RO Active low status bit indicates the fan tray is present
field:	6	A_PRES	- RO Active low status bit indicates power supply A is present
field:	5	B_PRES	- RO Active low status bit indicates power supply B is present
field:	4	PWR_OK	- RO Active high status bit indicates all pwr voltages are OK
field:	3	A_FAULT	- RO Active high status bit indicates a power supply A fault
field:	2	B_FAULT	- RO Active high status bit indicates a power supply B fault
field:	1	A_FAN_OK	- RO Active high status bit indicates power supply A fan is OK
field:	0	B_FAN_OK	- RO Active high status bit indicates power supply B fan is OK

[LE450CPLD_RST]
name: Reset Register, 0x3
width: 8
field:	7	-	0x0 RO Reserved
field:	6	FPGA	0x0 RW Active high reset for Lune FPGA
field:	5	PHY12	0x0 RW Active high reset for NNI phys
field:	4	PHY34	0x0 RW Active high reset for UNI phys
field:	3	PHY56	0x0 RW Active high reset for UNI phys
field:	2	PHY78	0x0 RW Active high reset for UNI phys
field:	1	PHY9A	0x0 RW Active high reset for UNI phys
field:	0	PHYBC	0x0 RW Active high reset for UNI phys

[LE450CPLD_RST2]
name: Reset Register 2, 0x4
width: 8
field:	7:4	-	0x0 RO Reserved
field:	3	PSB_SHUT_DN	0x0 RW Active high PSB_SHUT_DNN
field:	2	PSB_I2C_RST	0x0 RW Active high reset for PSB_I2C
field:	1	PSA_SHUT_DN	0x0 RW Active high PSA_SHUT_DNN
field:	0	PSA_I2C_RST	0x0 RW Active high reset for PSA_I2C

[LE450CPLD_I2C]
name: I2C Select Register, 0x5
width: 8
field:	7	PRMSK	0x0 RW Active high PCI Reset Mask
field:	6:0	I2C	0x0 RW I2C mux select lines

[LE450CPLD_FAN]
name: Fan Enables and Dying Gasp Register, 0x6
width: 8
field:	7:5	-	0x0 RO Reserved
field:	4	GASP	0x0 RW Logic sets this bit when a dying gasp interrupt occurs. It can also be written by software. Writing to this register disables the fan hardware sequencing until the next reset or fan tray insertion.
field:	3:0	FANS	0x0 RW Active high enable for fans 4-1 respectively. Logic sets these bits in a hardware controlled sequence following reset or when the fan tray is inserted. They are cleared when the fan tray is removed or a dying gasp interrupt occurs. They can also be written by software. Writing to this register disables the fan hardware sequencing until the next reset or fan tray insertion.

[LE450CPLD_FPP0]
name: FPP Status & PWR OK Register, 0x7
width: 8
field:	7	MODP	- RO Modular power supply
field:	6	FEEDA	- RO Feed A Good
field:	5	FEEDB	- RO Feed B Good
field:	4	NCFG	0x0 RW NCONFIG
field:	3	STS	0x0 RO STATUS
field:	2	CDONE	0x0 RO CONF_DONE
field:	1	IDONE	0x0 RO INIT_DONE
field:	0	CRC	0x0 RO CRC_ERR

[LE450CPLD_FPP1]
name: FPP Data Register, 0x8
width: 8
field:	7:0	FPP1	0x0 RW FPP Data

[LE450CPLD_ISR0]
name: Interrupt Status 0 Register, 0x9
width: 8
field:	7	FAN_PRES	0x0 WC Set high when fan tray presence bit changes state
field:	6	A_PRES	0x0 WC Set high when pwr supply A presence bit changes state
field:	5	B_PRES	0x0 WC Set high when pwr supply B presence bit changes state
field:	4	PWR_OK	0x0 WC Set high when power OK bit changes state
field:	3	A_FAULT	0x0 WC Set high when pwr supply A fault bit changes state
field:	2	B_FAULT	0x0 WC Set high when pwr supply B fault bit changes state
field:	1	A_FAN_OK	0x0 WC Set high when pwr supply A fan fail bit changes state
field:	0	B_FAN_OK	0x0 WC Set high when pwr supply B fan fail bit changes state

[LE450CPLD_MSK0]
name: Interrupt Mask 0 Register, 0xa
width: 8
field:	7	FAN_PRES	
field:	6	A_PRES	
field:	5	B_PRES	
field:	4	PWR_OK	
field:	3	A_FAULT	
field:	2	B_FAULT	
field:	1	A_FAN_OK	
field:	0	B_FAN_OK	

[LE450CPLD_TST0]
name: Interrupt Test 0 Register, 0xb
width: 8
field:	7	FAN_PRES	
field:	6	A_PRES	
field:	5	B_PRES	
field:	4	PWR_OK	
field:	3	A_FAULT	
field:	2	B_FAULT	
field:	1	A_FAN_OK	
field:	0	B_FAN_OK	

[LE450CPLD_SELF]
name: Self Reset Register, 0xc
width: 8
field:	7:0	SELF	0x0 WO Writing to this register causes a power on reset cycle. Data written is 0xDE.

[LE450CPLD_PWRC]
name: Power Cycle Register, 0xd
width: 8
field:	7:0	PWRC	0x0 WO Writing to this register causes the board power to shut down. Data written is 0xAD.

[LE450CPLD_LEDS]
name: LED Control Register, 0xe
width: 8
field:	7:6	-	0x0 RO Reserved
field:	5:3	ALARM	0x0 RW ALARM LED control
field:	2:0	STAT	0x0 RW STATUS LED control

