#!/bin/regdecode UIO Driver for Ciena LUNE FPGA

# LUNE Register Map and Register Definitions
# Rev 0.68

[LUNE_VER]
name: 0x0000    Version register
width: 16
field:	15:8	DSGN	0xAB R Design code specific to Lune
field:	7:4	MJR	0x1 R Major Version #
field:	3:0	MNR	0x0 R Minor Version #

[LUNE_ISR]
name: 0x0001    interrupt status register
width: 16
field:	15:14	-R1-	Reserved
field:	13	OISR    	Register assertion indicates one of 256 OAM services has completed.
field:	12	THERM_SD	Register assertion indicates assertion of therm_sdn pin into FPGA.
field:	11	TEMP1_ALERT	Register assertion indicates negation of temp1_alert_n pin into FPGA.
field:	10	TEMP1_CRIT	Register assertion indicates negation of temp1_crit_n pin into FPGA.
field:	9	TEMP2_ALERT	Register assertion indicates negation of temp2_alert_n pin into FPGA.
field:	8	TEMP2_CRIT	Register assertion indicates negation of temp2_crit_n pin into FPGA.
field:	7:4	-R3-	Reserved
field:	3	SFP	A change was detected in a ports SFP signals Present, Los, Txdefault since last read.
field:	2:0	-R2-	Reserved

[LUNE_ISM]
name: 0x0002    interrupt mask register
width: 16
field:	15:13	-R1-
field:	12	THERM_SD
field:	11	TEMP1_ALERT
field:	10	TEMP1_CRIT
field:	9	TEMP2_ALERT
field:	8	TEMP2_CRIT
field:	7:4	FANLOCK
field:	3	SFP
field:	2:0	-R2-

[LUNE_IST]
name: 0x0003    interrupt test register
width: 16
field:	15:13	-R1-
field:	12	THERM_SD
field:	11	TEMP1_ALERT
field:	10	TEMP1_CRIT
field:	9	TEMP2_ALERT
field:	8	TEMP2_CRIT
field:	7:4	FANLOCK
field:	3	SFP
field:	2:0	-R2-

[LUNE_ISB]
name: 0x0004    interrupt test register
width: 16
field:	15:0	BLOCK	0x0 R/W SW writes this register with those bits set that it wishes to hide the interrupt status bit for.

[LUNE_IGREN]
name: 0x0005    receive interface enable register
width: 16
field:	15:12	UI3-0	0x0 R/W UNI Ports 3-0, see NNI port 0 below
field:	11	NE3IE	0x0 R/W NNI Port 3 Ingress Interface Enable (box RX path)
value:		0	Disabled	All input frame data blocked from FPGA
value:		1	Enabled		Input frame data passed to FPGA
field:	10	NE2IE	0x0 R/W NNI Port 2 Ingress Interface Enable (box RX path)
value:		0	Disabled	All input frame data blocked from FPGA
value:		1	Enabled		Input frame data passed to FPGA
field:	9	NE1IE	0x0 R/W NNI Port 1 Ingress Interface Enable (box RX path)
value:		0	Disabled	All input frame data blocked from FPGA
value:		1	Enabled		Input frame data passed to FPGA
field:	8	NE0IE	0x0 R/W NNI Port 0 Ingress Interface Enable (box RX path)
value:		0	Disabled	All input frame data blocked from FPGA
value:		1	Enabled		Input frame data passed to FPGA
field:	7:4	UE3-0	0x0 R/W UNI Ports 3-0, see NNI port 0 below
field:	3	NE3PE	0x0 R/W NNI Port 3 Ingress Processing Enable (box RX path)
value:		0	Bypass	All frames are passed through unmodified, regardless of other settings.
value:		1	On	Port Configuration settings in effect
field:	2	NE2PE	0x0 R/W NNI Port 2 Ingress Processing Enable (box RX path)
value:		0	Bypass	All frames are passed through unmodified, regardless of other settings.
value:		1	On	Port Configuration settings in effect
field:	1	NE1PE	0x0 R/W NNI Port 1 Ingress Processing Enable (box RX path)
value:		0	Bypass	All frames are passed through unmodified, regardless of other settings.
value:		1	On	Port Configuration settings in effect
field:	0	NE0PE	0x0 R/W NNI Port 0 Ingress Processing Enable (box RX path)
value:		0	Bypass	All frames are passed through unmodified, regardless of other settings.
value:		1	On	Port Configuration settings in effect

[LUNE_EGREN]
name: 0x0006    transmit inteface enable register
width: 16
field:	15:12	-R1-	0x0 --- Reserved
field:	11	NE3IE	0x0 R/W NNI Port 3 Egress Interface Enable (box TX path)
value:		0	Disabled	All input frame data blocked from FPGA
value:		1	Enabled		Input frame data passed to FPGA
field:	10	NE2IE	0x0 R/W NNI Port 2 Egress Interface Enable (box TX path)
value:		0	Disabled	All input frame data blocked from FPGA
value:		1	Enabled		Input frame data passed to FPGA
field:	9	NE1IE	0x0 R/W NNI Port 1 Egress Interface Enable (box TX path)
value:		0	Disabled	All input frame data blocked from FPGA
value:		1	Enabled		Input frame data passed to FPGA
field:	8	NE0IE	0x0 R/W NNI Port 0 Egress Interface Enable (box TX path)
value:		0	Disabled	All input frame data blocked from FPGA
value:		1	Enabled		Input frame data passed to FPGA
field:	7:4	-R2-	0x0 --- Reserved
field:	3	NE3PE	0x0 R/W NNI Port 3 Egress Processing Enable (box TX path)
value:		0	Bypass	All frames are passed through unmodified, regardless of other settings.
value:		1	On	Port Configuration settings in effect
field:	2	NE2PE	0x0 R/W NNI Port 2 Egress Processing Enable (box TX path)
value:		0	Bypass	All frames are passed through unmodified, regardless of other settings.
value:		1	On	Port Configuration settings in effect
field:	1	NE1PE	0x0 R/W NNI Port 1 Egress Processing Enable (box TX path)
value:		0	Bypass	All frames are passed through unmodified, regardless of other settings.
value:		1	On	Port Configuration settings in effect
field:	0	NE0PE	0x0 R/W NNI Port 0 Egress Processing Enable (box TX path)
value:		0	Bypass	All frames are passed through unmodified, regardless of other settings.
value:		1	On	Port Configuration settings in effect

[LUNE_VETM]
name: 0x0007    VLAN etype mode
width: 16
field:	15:12	P3	0x0 R/W Port 3 modes, See port 0 definitions below [3:0]
field:	11:8	P2	0x0 R/W Port 2 modes, See port 0 definitions below [3:0]
field:	7:4	P1	0x0 R/W Port 1 modes, See port 0 definitions below [3:0]
field:	3	----	0x0 R Reserved
field:	2	MD	0x0 --- Remark all E-types Mode – Port 0 When port’s vlan-ether-type is set to 0x9100, this bit defines how that alternate etype is used:
value:		0	service		Mark only “service” vlans with 0x9100
value:		1	outermost	Mark all outermost VLANs with 0x9100 (including MPLS  transport vlans).
field:	1:0	TYPE	0x0 R/W Service VLAN Etype port 0
value:		0	x8100 Etype
value:		1	x9100 Etype
value:		2	x88A8 Etype
value:		3	Reserved for future use

[LUNE_SWAP_ETYP]
name: 0x0008    global internal swap-ethertype for MPLS "transit" traffic
width: 16
field:	15:0	STYPE	0x8850 R/W This Register holds the value used by the hardware to modify the MPLS ETYPE on an ingressing swap frame.  This ETYPE is later used by the hardware to differentiate swap frames from regular MPLS frames at egress.  No frames are sent out of the box with this ETYPE.
value:		0x8850	default

[LUNE_EFBT]
name: 0x0009    egress frame buffer threshold register
width: 16
field:	15:11	----	0x0 R Reserved
field:	10:0	UTHR	0x7FF R/W Lower Threshold, point at which an XON request is made, default is half the buffer.

[LUNE_PAUS]
name: 0x000A    pause quanta to send when backpressuring local switch
width: 16
field:	15:8	----	0x0 R Reserved
field:	7:0	PAUS	0x0 R/W Pause Quanta sent to VIA when applying backpressure.  This register should be set relative to the upper flow control threshold.

[LUNE_OAM_TWP_ERR_EST]
name: 0x000B    OAM TWAMP Error Estimate
width: 16
field:	15:0	EEST	0x0 R/W TWAMP Error Estimate. An estimate of clock and synchronization error. Gets added to all TWAMP reflected frames.

[LUNE_OAMC]
name: 0x000C    OAM timer-scan interval and mode controls
width: 16
field:	15:4	TSCNT	0xCB5 R/W OAM Timer Scan 3.33ms count control setting  3.33mS /(256 * clk-period)
value:		0xCB5	Lune	(3253) clk-period is 4ns
value:		0xA2A	Sirion	(2602) clk-period is 5ns
field:	3	--	0x0 R/W Reserved
field:	2	SM	0x0 R/W OAM Sequence Number Master Select
value:		0	local source for Sequence No. Generator
value:		1	external source for Sequence No. Generator
field:	1	SE	0x0 R/W OAM Profile Table, Service Scan Enable
field:	0	TE	0x0 R/W OAM Profile Table, Timer Scan Enable

[LUNE_TTL]
name: 0x000D    static TTL used for both Tunnels and VC's
width: 16
field:	15:8	TNL_TTL	0xFF R/W Default TTL value to use with Tunnel Label Stack Entries during MPLS encapsulation
field:	7:0	VC_TTL	0xFF R/W Default TTL value to use with VC Label Stack Entries during MPLS encapsulation

[LUNE_DOT1_ETYP]
name: 0x000E    global .1ag ethertype
width: 16
field:	15:0	ETYPE	0x8902 R/W This Register holds the value used by the hardware to identify Y-1731 frames

[LUNE_BVID_ETYP]
name: 0x000F    global bvid etype
width: 16
field:	15:0	ETYPE	0x88A8 R/W This Register holds the value used by the hardware to identify PBT B-VIDs

[LUNE_ISID_ETYP]
name: 0x0010    global isid etype
width: 16
field:	15:0	ETYPE	0x88C8 R/W This Register holds the value used by the hardware to identify PBT I-SIDs

[LUNE_ICFM_ETYP]
name: 0x0011    global ingress CFM etype
width: 16
field:	15:0	ETYPE	0x8902 R/W This Register holds the value used by the hardware to identify 802.1ag CFM frames on ingress (RX)

[LUNE_ECFM_ETYP]
name: 0x0012    global egress CFM etype
width: 16
field:	15:0	ETYPE	0x88B8 R/W This Register holds the value used by the hardware to identify PBT CFM frames on egress (TX), which in turn need to be converted to the value stored in the register: TLS_BVID_ETYPE.

[LUNE_1588_ETYP]
name: 0x0013    global 1588v2 ethertype
width: 16
field:	15:0	ETYPE	0x1234 R/W This Register holds the value used by the hardware to identify IEEE1588v2 frames on ingress

[LUNE_DIAG_CTL]
name: 0x0014    DIAGNOSTIC Control
width: 16
field:	15:12	--	-- -- reserved
field:	11:8	DiagSel	0x0 R/W Diagnostic select.  This control maps diagnostic signals to external pins according to the matrix shown below in Table 37: Diagnostic Select Pin Routing.
field:	7:4	PHYLB	0x0 R/W Setting these bits enable LVDS GMII level loopback on the PHY side.  Each bit corresponds to a port location:
value:		7	port3
value:		6	port2
value:		5	port1
value:		4	port0
field:	3:0	MACLB	0x0 R/W Setting these bits enable LVDS GMII level loopback on the MAC side.  Each bit corresponds to a port location:
value:		3	port3
value:		2	port2
value:		1	port1
value:		0	port0

[LUNE_FAN_PWM]
name: 0x0015    Fan Pulse Width Modulation Register
width: 16
field:	15:5	----	0x0 R Reserved
field:	4:0	FAN_PWM	0x1F R/W Changes the speed of all fans by adjusting the duty cycle of a 20Khz gnerated waveform.

[LUNE_FAN0_TACH]
name: 0x0016    Fan 0 Tachometer
width: 16
field:	15:8	----	0x0 R Reserved
field:	7:0	TACH	0x0 R The count in this register indicates the number of 180 degress revolutions of fan 0 in the previous sampled 64ms interval.

[LUNE_FAN1_TACH]
name: 0x0017    Fan 1 Tachometer
width: 16
field:	15:8	----	0x0 R Reserved
field:	7:0	TACH	0x0 R The count in this register indicates the number of 180 degress revolutions of fan 0 in the previous sampled 64ms interval.

[LUNE_FAN2_TACH]
name: 0x0018    Fan 2 Tachometer
width: 16
field:	15:8	----	0x0 R Reserved
field:	7:0	TACH	0x0 R The count in this register indicates the number of 180 degress revolutions of fan 0 in the previous sampled 64ms interval.

[LUNE_FAN3_TACH]
name: 0x0019    Fan 3 Tachometer
width: 16
field:	15:8	----	0x0 R Reserved
field:	7:0	TACH	0x0 R The count in this register indicates the number of 180 degress revolutions of fan 0 in the previous sampled 64ms interval.

[LUNE_OISR_L1]
name: 0x001A    OAM ISR Level 1
width: 16
field:	15:0	OISR_L1	0x0 R Each bit in this Register indicates that at lease on of 16 bits in the associated segment of the 256 bit OAM int status reg is asserted.

[LUNE_OISR_L2CTL]
name: 0x001B    OAM ISR Level 2 control
width: 16
field:	15:5	----	0x0 R Reserved
field:	4	WRT   0x0 R/W When asserted, this bit forces a clear of specified bits of the 256 bit OAM int status reg
field:	3:0	ADDR  0x0 R/W This field select one of 16 segments in the 256 bit OAM int status reg.

[LUNE_OISR_L2CLR]
name: 0x001C    OAM ISR Level 2 Clear
width: 16
field:	15:0	CLR  0x0 R/W When written with OISR_L2W asserted, each asserted bit in this reg will force a clear of a corresponding bin in the 256 bit OAM int status reg.

[LUNE_OISR_L2DAT]
name: 0x001D    OAM ISR Level 2 data
width: 16
field:	15:0	DATA 0x0 R Contains one of 16 segments in the 256 bit OAM int status reg.

pad: 2

[LUNE_QDRII]
name: 0x001F    SFP QDRII Register 2
width: 16
field:	15	TERR	0x0 R Training ERROR
value:		0	Okay
value:		1	Failed to train QDRII SRAM interface
field:	14	TDON	Training Done
value:		0	Training in progress
value:		1	Done Training
field:	13	--R1--	0x0 R Reserved
field:	12:8	LATENCY	0x12 R QDRII read latency from RPS_N to RDY
field:	7	--R2--	0x0 R Reserved
field:	6	BFAIL	0x0 R Bist Failed
value:		0	Successful BIST
value:		1	Failed BIST , at least one location that did not read back correctly.
field:	5	BIP	0x0 R Bist In Progress
value:		0	complete BIST , QDRII can be enabled
value:		1	running BIST (currently a 2mS duration)
field:	4	BTRG	0x0 W Bist Trigger
field:	3:1	--R3--	0x0 R Reserved
field:	0	DOFN	0x1 R DOFFn state.

[LUNE_SFPD0]
name: 0x0020    SFP Disable Register 0
width: 16
field:	15:0	USFPD[15_0]	0xFFFF R/W Assertion of bits will disable external SFP board components with UNI port numbers corresponding to the bit index.

[LUNE_SFPD1]
name: 0x0021    SFP Disable Register 1
width: 16
field:	15:8	-	0x00 R Reserved.
field:	7:4	NSFPD[3_0]	0xF R/W Assertion of bits will disable external SFP board components with NNI port numbers corresponding to the bit index.
field:	3:0	USFPD[19_16]	0xF R/W Assertion of bits will disable external SFP board components with UNI port numbers corresponding to the bit index.

[LUNE_LED0]
name: 0x0022    LED Register 0
width: 16
field:	15:0	USFPL[15_0]	0x0000 R/W Assertion of bits will illuminate board LED’s representing to UNI port numbers corresponding to the field bit index.

[LUNE_LED1]
name: 0x0023    LED Register 1
width: 16
field:	15:10	-	0x00 R Reserved.
field:	9	TLY	0x00 R Assertion of this will illuminate board LED representing temperature has a yellow value.
field:	8	TLG	0x00 R Assertion of this will illuminate board LED representing temperature has a green value.
field:	7:4	NSFPL[3_0]	0x0 R/W Assertion of bits will illuminate board LED’s representing to NNI port numbers corresponding to the field bit index.
field:	3:0	USFPL[19_16]	0x0 R/W Assertion of bits will illuminate board LED’s representing to UNI port numbers corresponding to the field bit index.

[LUNE_SFPP0]
name: 0x0024    SFP Present and Change Register 0
width: 16
field:	15:8	USFPPC[7_0]	0x00 R Assertion of bits indicates a change, since last read, in de-bounced present signal in UNI SFP port number corresponding to the field bit index.
field:	7:0	USFPP[7_0]	0x00 R Assertion of bits indicates de-bounced present signal in UNI SFP port number corresponding to the field bit index.

[LUNE_SFPP1]
name: 0x0025    SFP Present and Change Register 1
width: 16
field:	15:8	USFPPC[15_8]	0x00 R Assertion of bits indicates a change, since last read, in de-bounced present signal in UNI SFP port number corresponding to the field bit index.
field:	7:0	USFPP[15_8]	0x00 R Assertion of bits indicates de-bounced present signal in UNI SFP port number corresponding to the field bit index.

[LUNE_SFPP2]
name: 0x0026    SFP Present and Change Register 2
width: 16
field:	15:12	NSFPPC[3_0]	0x0 R Assertion of bits indicates a change, since last read, in de-bounced present signal in NNI SFP port number corresponding to the field bit index.
field:	11:8	USFPPC[19_16]	0x0 R Assertion of bits indicates a change, since last read, in de-bounced present signal in UNI SFP port number corresponding to the field bit index.
field:	7:4	NSFPP[3_0]	0x0 R Assertion of bits indicates de-bounced present signal in NNI SFP port number corresponding to the field bit index.
field:	3:0	USFPP[19_16]	0x0 R Assertion of bits indicates de-bounced present signal in UNI SFP port number corresponding to the field bit index.

[LUNE_SFPL0]
name: 0x0027    SFP Los     and Change Register 0
width: 16
field:	15:8	USFPLC[7_0]	0x00 R Assertion of bits indicates a change, since last read, in Los signal in UNI SFP port number corresponding to the field bit index.
field:	7:0	USFPL[7_0]	0x00 R Assertion of bits indicates Los signal in UNI SFP port number corresponding to the field bit index.

[LUNE_SFPL1]
name: 0x0028    SFP Los     and Change Register 1
width: 16
field:	15:8	USFPLC[15_8]	0x00 R Assertion of bits indicates a change, since last read, in Los signal in UNI SFP port number corresponding to the field bit index.
field:	7:0	USFPL[15_8]	0x00 R Assertion of bits indicates Los signal in UNI SFP port number corresponding to the field bit index.

[LUNE_SFPL2]
name: 0x0029    SFP Los     and Change Register 2
width: 16
field:	15:12	NSFPLC[3_0]	0x0 R Assertion of bits indicates a change, since last read, in Los signal in NNI SFP port number corresponding to the field bit index.
field:	11:8	USFPLC[19_16]	0x0 R Assertion of bits indicates a change, since last read, in Los signal in UNI SFP port number corresponding to the field bit index.
field:	7:4	NSFPL[3_0]	0x0 R Assertion of bits indicates Los signal in NNI SFP port number corresponding to the field bit index.
field:	3:0	USFPL[19_16]	0x0 R Assertion of bits indicates  Los signal in UNI SFP port number corresponding to the field bit index.

[LUNE_SFPF0]
name: 0x002A    SFP TxFault and Change Register 0
width: 16
field:	15:8	USFPFC[7_0]	0x00 R Assertion of bits indicates a change, since last read, in TxFault signal in UNI SFP port number corresponding to the field bit index.
field:	7:0	USFPF[7_0]	0x00 R Assertion of bits indicates TxFault signal in UNI SFP port number corresponding to the field bit index.

[LUNE_SFPF1]
name: 0x002B    SFP TxFault and Change Register 1
width: 16
field:	15:8	USFPFC[15_8]	0x00 R Assertion of bits indicates a change, since last read, in TxFault signal in UNI SFP port number corresponding to the field bit index.
field:	7:0	USFPF[15_8]	0x00 R Assertion of bits indicates TxFault signal in UNI SFP port number corresponding to the field bit index.

[LUNE_SFPF2]
name: 0x002C    SFP TxFault and Change Register 2
width: 16
field:	15:12	NSFPFC[3_0]	0x0 R Assertion of bits indicates a change, since last read, in TxFault signal in NNI SFP port number corresponding to the field bit index.
field:	11:8	USFPFC[19_16]	0x0 R Assertion of bits indicates a change, since last read, in TxFault signal in UNI SFP port number corresponding to the field bit index.
field:	7:4	NSFPF[3_0]	0x0 R Assertion of bits indicates TxFault signal in NNI SFP port number corresponding to the field bit index.
field:	3:0	USFPF[19_16]	0x0 R Assertion of bits indicates TxFault signal in UNI SFP port number corresponding to the field bit index.

[LUNE_SFPM0]
name: 0x002D    SFP Mask               Register 0
width: 16
field:	15:0	USFPPM[15_0]	0x0000 R Assertion of bits disable the ability of a change in Present signal, in UNI SFP port number corresponding to the field bit index, to create an Interrupt.

[LUNE_SFPM1]
name: 0x002E    SFP Mask               Register 1
width: 16
field:	15:8	-----------	0x0 R/W Reserved
field:	7:4	NSFPPM[3_0]	0x0 R Assertion of bits disable the ability of a change in Present signal, in NNI SFP port number corresponding to the field bit index, to create an Interrupt.
field:	3:0	USFPPM[19_16]	0x0 R Assertion of bits disable the ability of a change in Present signal, in UNI SFP port number corresponding to the field bit index, to create an Interrupt.

[LUNE_SFPM2]
name: 0x002F    SFP Mask               Register 2
width: 16
field:	15:0	USFPLM[15_0]	0x0000 R Assertion of bits disable the ability of a change in Los signal, in UNI SFP port number corresponding to the field bit index, to create an Interrupt.

[LUNE_SFPM3]
name: 0x0030    SFP Mask               Register 3
width: 16
field:	15:8	-----------	0x0 R/W Reserved
field:	7:4	NSFPLM[3_0]	0x0 R Assertion of bits disable the ability of a change in Los signal, in NNI SFP port number corresponding to the field bit index, to create an Interrupt.
field:	3:0	USFPLM[19_16]	0x0 R Assertion of bits disable the ability of a change in Los signal, in UNI SFP port number corresponding to the field bit index, to create an Interrupt.

[LUNE_SFPM4]
name: 0x0031    SFP Mask               Register 4
width: 16
field:	15:0	USFPFM[15_0]	0x0000 R Assertion of bits disable the ability of a change in TxFault signal, in UNI SFP port number corresponding to the field bit index, to create an Interrupt.

[LUNE_SFPM5]
name: 0x0032    SFP Mask               Register 5
width: 16
field:	15:8	-----------	0x0 R/W Reserved
field:	7:4	NSFPFM[3_0]	0x0 R Assertion of bits disable the ability of a change in TxFault signal, in NNI SFP port number corresponding to the field bit index, to create an Interrupt.
field:	3:0	USFPFM[19_16]	0x0 R Assertion of bits disable the ability of a change in TxFault signal, in UNI SFP port number corresponding to the field bit index, to create an Interrupt.

[LUNE_PFDET]
name: 0x0033    OAM Profile change detect
width: 16

[LUNE_PID_0]
name: 0x0034    OAM Profile ID 0
width: 16

[LUNE_PID_1]
name: 0x0035    OAM Profile ID 1
width: 16

[LUNE_PID_2]
name: 0x0036    OAM Profile ID 2
width: 16

[LUNE_PID_3]
name: 0x0037    OAM Profile ID 3
width: 16

pad: 16

[LUNE_RTC_CTRL]
name: 0x0040    realtime clock control register
width: 16
field:	15:3	----	0x0 R/W Reserved
field:	2	EN	0x0 R/W RTC Enable.
value:		0	hold RTC at current value;
value:		1	normal operation.
field:	1	CLR	0x0 R/W On write, this bit is RTC Clear.
value:		1	clear RTC
field:	0	SEL	0x0 R/W RTC Select. Selects between the locally-generated or remote RTC.
value:		0	local
value:		1	remote

[LUNE_RTC0]
name: 0x0041    realtime clock register [15:0]
width: 16
field:	15:0	RTC0	0x0 R RTC[15:0]. Must be the first of the four RTC registers read.

[LUNE_RTC1]
name: 0x0042    realtime clock register [31:16]
width: 16
field:	15:0	RTC0	0x0 R RTC[31:16]

[LUNE_RTC2]
name: 0x0043    realtime clock register [47:32]
width: 16
field:	15:0	RTC0	0x0 R RTC[47:32]

[LUNE_RTC3]
name: 0x0044    realtime clock register [63:48]
width: 16
field:	15:0	RTC0	0x0 R RTC[63:48]

[LUNE_RTC_OFST0]
name: 0x0045    realtime clock offset register [15:0]
width: 16
field:	15:0	OFST0	0x0 R/W RTC Offset [15:0].

[LUNE_RTC_OFST1]
name: 0x0046    realtime clock offset register [31:16]
width: 16
field:	15:0	OFST1	0x0 R/W RTC Offset [31:16].

[LUNE_RTC_OFST2]
name: 0x0047    realtime clock offset register [47:32]
width: 16
field:	15:0	OFST2	0x0 R/W RTC Offset [47:32].

[LUNE_RTC_OFST3]
name: 0x0048    realtime clock offset register [63:48]
width: 16
field:	15:0	OFST3	0x0 R/W RTC Offset [63:48].

[LUNE_RTC_OFST_CNT0]
name: 0x0049    realtime clock offset count register [15:0]
width: 16
field:	15:0	OCNT0	0x0 R/W RTC Offset Count [15:0]. Lower 16 bits of 20-bit offset count register.

[LUNE_RTC_OFST_CNT1]
name: 0x004A    realtime clock offset count register [19:16]
width: 16
field:	15	OSGN	0x0 R/W RTC Offset Sign.
value:		0	Positive	(add offset to current RTC value)
value:		1	Negative	(subtract offset from current RTC value)
field:	14	OGO	0x0 R/W On write, this bit is RTC Offset Go.
value:		1	start offset operation
field:	13:4	----	0x0 R Reserved
field:	3:0	OCNT1	0x0 R/W RTC Offset Count [19:16]. Upper 4 bits of 20-bit offset count register.

[LUNE_RTC_DRFT]
name: 0x004B    realtime clock drift adjust register
width: 16
field:	15:10	----	0x0 R Reserved
field:	9	DSGN	0x0 R/W RTC Drift Sign.
value:		0	Positive	(speeds up the RTCrate of count)
value:		1	Negative	(slows down the RTC rate of count).
field:	8:0	DRFT	0x0 R/W RTC Drift Correction. Magnitude of RTC drift correction to apply, in units of 0.296ppm.

[LUNE_RTC_1588_0]
name: 0x004C    realtime 1588 clock register [15:0]
width: 16

[LUNE_RTC_1588_1]
name: 0x004D    realtime 1588 clock register [31:16]
width: 16

[LUNE_RTC_1588_2]
name: 0x004E    realtime 1588 clock register [47:32]
width: 16

[LUNE_RTC_1588_3]
name: 0x004F    realtime 1588 clock register [63:48]
width: 16

[LUNE_RTC_EPO_OFST0]
name: 0x0050    NTP to 1588 Epoch offset register [15:0]
width: 16

[LUNE_RTC_EPO_OFST1]
name: 0x0051    NTP to 1588 Epoch offset register [31:16]
width: 16

pad: 92

[LUNE_INDX_SEL]
name: 0x0080    table index select register
width: 16
field:	15	ERR	0x0 R Error occurred during operation, i.e. Write to LUNE_INDX register while AIP is set
field:	14	AIP	0x0 R
value:		0	Done	Access complete or no-access in progress (done)
value:		1	inProg	Access in Progress
field:	13	RW	0x0 R/W Read = 1, Write = 0
field:	12:8	----	0x0 R Reserved
field:	7:0	SEL	0x0 R/W Table select (refer to Table 38)

[LUNE_INDX0]
name: 0x0081    table index register
width: 16
field:	15:0	ADDR15_0	0x0 R/W Address to access

[LUNE_INDX1]
name: 0x0082    table index register
width: 16
field:	15:0	ADDR31_16	0x0 R/W Address to access

[LUNE_DAT0]
name: 0x0083    table data 0 register
width: 16

[LUNE_DAT1]
name: 0x0084    table data 1 register
width: 16

[LUNE_DAT2]
name: 0x0085    table data 2 register
width: 16

[LUNE_DAT3]
name: 0x0086    table data 3 register
width: 16

[LUNE_DAT4]
name: 0x0087    table data 4 register
width: 16

[LUNE_DAT5]
name: 0x0088    table data 5 register
width: 16

[LUNE_DAT6]
name: 0x0089    table data 6 register
width: 16

[LUNE_DAT7]
name: 0x008A    table data 7 register
width: 16

[LUNE_DAT8]
name: 0x008B    table data 8 register
width: 16

pad: 232

[LUNE_U0_CNFG]
name: 0x0100    uplink 0 configuration register
width: 16
field:	15:14	LPRT	0x0 R/W Logical Port Designation, default MUST match physical port. Valid values are {0-3}
field:	13:12	SPEED	0x0 R/W Port speed.
value:		0	1Gb
value:		1	100Mb
value:		2	10Mb
field:	11	TCT	0x0 R/W Transparent Control Frame Tunneling
value:		0	ALL	port supports martini decap of all control frames except pause frames.
value:		1	CTRL	port only allows martini decap of Cisco-WWP control frames
field:	10	-R1-	0x0 R Reserved for future use
field:	9	UTM	0x0 R/W Untagged Mode
value:		0	accept all
value:		1	drop untagged
field:	8	FCE	0x0 R/W Ingress Flow Control Enable
value:		0	Drop	port will drop received 802.3x frames
value:		1	Pass	port will pass received 802.3x frames
field:	7	DRP	0x0 R/W Ingress Transport Drop Mode
value:		0	Pass frames that have unknown Tunnel
value:		1	Drop frames that have unknown Tunnel
field:	6	AM	0x0 R/W ARP Mode
value:		0	police		allow ARP frames to be policed, per police mode
value:		1	do_not_police	do not allow ARP frames to be policed
field:	5	PM	0x0 R/W Police Mode
value:		0	off
value:		1	on
field:	4	FAM	0x0 R/W Frame Accounting Mode
value:		0	Include Minimum IFG in Policing math
value:		1	Do not include Minimum IFG in Policing math
field:	3	EOL	0x0 R/W EOAM loop back enable
value:	0	Disabled
value:	1	Enabled	All frames will be in loopback mode except EOAM PDU
field:	2	DPS	0x0 R/W Disable priority tag stripping
value:		0	Enable	Priority tagged stripping
value:		1	Disable	Priority tagged stripping
field:	1	MR	0x0 R/W ING_COS Mapping MISS Re-Assess Mode
value:		0	do not re-assess  (map) using frame’s .1D priority
value:		1	re-assess (map) using frame’s .1D priority
field:	0	MD	0x0 R/W ING_COS Mapping MISS Drop Mode
value:		0	drop frame
value:		1	port-based default CoS setting

[LUNE_U0_DFLT]
name: 0x0101    uplink 0 default meter designation
width: 16
field:	15:10	----	0x0 R Reserved for future use
field:	9:0	DSVC	0x0 R/W Default Service Level for non-matching frames

[LUNE_U0_DVLN]
name: 0x0102    uplink 0 default vlan
width: 16
field:	15:13	PRI	0x0 R/W D-PRI
field:	12	----	0x0 R/W Reserved for future use
field:	11:0	VID	0x0 R/W D-VID

[LUNE_U0_DTOS]
name: 0x0103    uplink 0 default tos
width: 16
field:	15:7	---	--- R Reserved
field:	6	VLD	0x0 R/W DSCP is valid
value:		0	invalid	yet to be configured
value:		1	valid	can be used for remarking no-match TOS
field:	5:0	DTOS	0x0 R/W Default DSCP/IPP value for “stomping” TOS when mapping is found to be invalid.

[LUNE_U0_CFIE]
name: 0x0104    uplink 0 arp     meter designation
width: 16
field:	15:8	----	0x0 R/W Reserved, must be left ‘0’
field:	7:0	CFIE	0x0 R/W Each bit provides a per-service level enable for using the CFI bit as a policing result indicator.

[LUNE_U0_ARPS]
name: 0x0105    uplink 0 arp     meter designation
width: 16
field:	15:10	----	0x0 R Reserved for future use
field:	9:0	ASVC	0x0 R/W Service Level to “police” ARPs with

pad: 500

[LUNE_U1_CNFG]
name: 0x0200    uplink 0 configuration register
width: 16
field:	15:14	LPRT	0x0 R/W Logical Port Designation, default MUST match physical port. Valid values are {0-3}
field:	13:12	SPEED	0x0 R/W Port speed.
value:		0	1Gb
value:		1	100Mb
value:		2	10Mb
field:	11	TCT	0x0 R/W Transparent Control Frame Tunneling
value:		0	ALL	port supports martini decap of all control frames except pause frames.
value:		1	CTRL	port only allows martini decap of Cisco-WWP control frames
field:	10	-R1-	0x0 R Reserved for future use
field:	9	UTM	0x0 R/W Untagged Mode
value:		0	accept all
value:		1	drop untagged
field:	8	FCE	0x0 R/W Ingress Flow Control Enable
value:		0	Drop	port will drop received 802.3x frames
value:		1	Pass	port will pass received 802.3x frames
field:	7	DRP	0x0 R/W Ingress Transport Drop Mode
value:		0	Pass frames that have unknown Tunnel
value:		1	Drop frames that have unknown Tunnel
field:	6	AM	0x0 R/W ARP Mode
value:		0	police		allow ARP frames to be policed, per police mode
value:		1	do_not_police	do not allow ARP frames to be policed
field:	5	PM	0x0 R/W Police Mode
value:		0	off
value:		1	on
field:	4	FAM	0x0 R/W Frame Accounting Mode
value:		0	Include Minimum IFG in Policing math
value:		1	Do not include Minimum IFG in Policing math
field:	3	EOL	0x0 R/W EOAM loop back enable
value:	0	Disabled
value:	1	Enabled	All frames will be in loopback mode except EOAM PDU
field:	2	DPS	0x0 R/W Disable priority tag stripping
value:		0	Enable	Priority tagged stripping
value:		1	Disable	Priority tagged stripping
field:	1	MR	0x0 R/W ING_COS Mapping MISS Re-Assess Mode
value:		0	do not re-assess  (map) using frame’s .1D priority
value:		1	re-assess (map) using frame’s .1D priority
field:	0	MD	0x0 R/W ING_COS Mapping MISS Drop Mode
value:		0	drop frame
value:		1	port-based default CoS setting

[LUNE_U1_DFLT]
name: 0x0201    uplink 0 default meter designation
width: 16
field:	15:10	----	0x0 R Reserved for future use
field:	9:0	DSVC	0x0 R/W Default Service Level for non-matching frames

[LUNE_U1_DVLN]
name: 0x0202    uplink 0 default vlan
width: 16
field:	15:13	PRI	0x0 R/W D-PRI
field:	12	----	0x0 R/W Reserved for future use
field:	11:0	VID	0x0 R/W D-VID

[LUNE_U1_DTOS]
name: 0x0203    uplink 0 default tos
width: 16
field:	15:7	---	--- R Reserved
field:	6	VLD	0x0 R/W DSCP is valid
value:		0	invalid	yet to be configured
value:		1	valid	can be used for remarking no-match TOS
field:	5:0	DTOS	0x0 R/W Default DSCP/IPP value for “stomping” TOS when mapping is found to be invalid.

[LUNE_U1_CFIE]
name: 0x0204    uplink 0 arp     meter designation
width: 16
field:	15:8	----	0x0 R/W Reserved, must be left ‘0’
field:	7:0	CFIE	0x0 R/W Each bit provides a per-service level enable for using the CFI bit as a policing result indicator.

[LUNE_U1_ARPS]
name: 0x0205    uplink 0 arp     meter designation
width: 16
field:	15:10	----	0x0 R Reserved for future use
field:	9:0	ASVC	0x0 R/W Service Level to “police” ARPs with

pad: 500

[LUNE_U2_CNFG]
name: 0x0300    uplink 0 configuration register
width: 16
field:	15:14	LPRT	0x0 R/W Logical Port Designation, default MUST match physical port. Valid values are {0-3}
field:	13:12	SPEED	0x0 R/W Port speed.
value:		0	1Gb
value:		1	100Mb
value:		2	10Mb
field:	11	TCT	0x0 R/W Transparent Control Frame Tunneling
value:		0	ALL	port supports martini decap of all control frames except pause frames.
value:		1	CTRL	port only allows martini decap of Cisco-WWP control frames
field:	10	-R1-	0x0 R Reserved for future use
field:	9	UTM	0x0 R/W Untagged Mode
value:		0	accept all
value:		1	drop untagged
field:	8	FCE	0x0 R/W Ingress Flow Control Enable
value:		0	Drop	port will drop received 802.3x frames
value:		1	Pass	port will pass received 802.3x frames
field:	7	DRP	0x0 R/W Ingress Transport Drop Mode
value:		0	Pass frames that have unknown Tunnel
value:		1	Drop frames that have unknown Tunnel
field:	6	AM	0x0 R/W ARP Mode
value:		0	police		allow ARP frames to be policed, per police mode
value:		1	do_not_police	do not allow ARP frames to be policed
field:	5	PM	0x0 R/W Police Mode
value:		0	off
value:		1	on
field:	4	FAM	0x0 R/W Frame Accounting Mode
value:		0	Include Minimum IFG in Policing math
value:		1	Do not include Minimum IFG in Policing math
field:	3	EOL	0x0 R/W EOAM loop back enable
value:	0	Disabled
value:	1	Enabled	All frames will be in loopback mode except EOAM PDU
field:	2	DPS	0x0 R/W Disable priority tag stripping
value:		0	Enable	Priority tagged stripping
value:		1	Disable	Priority tagged stripping
field:	1	MR	0x0 R/W ING_COS Mapping MISS Re-Assess Mode
value:		0	do not re-assess  (map) using frame’s .1D priority
value:		1	re-assess (map) using frame’s .1D priority
field:	0	MD	0x0 R/W ING_COS Mapping MISS Drop Mode
value:		0	drop frame
value:		1	port-based default CoS setting


[LUNE_U2_DFLT]
name: 0x0301    uplink 0 default meter designation
width: 16
field:	15:10	----	0x0 R Reserved for future use
field:	9:0	DSVC	0x0 R/W Default Service Level for non-matching frames

[LUNE_U2_DVLN]
name: 0x0302    uplink 0 default vlan
width: 16
field:	15:13	PRI	0x0 R/W D-PRI
field:	12	----	0x0 R/W Reserved for future use
field:	11:0	VID	0x0 R/W D-VID

[LUNE_U2_DTOS]
name: 0x0303    uplink 0 default tos
width: 16
field:	15:7	---	--- R Reserved
field:	6	VLD	0x0 R/W DSCP is valid
value:		0	invalid	yet to be configured
value:		1	valid	can be used for remarking no-match TOS
field:	5:0	DTOS	0x0 R/W Default DSCP/IPP value for “stomping” TOS when mapping is found to be invalid.

[LUNE_U2_CFIE]
name: 0x0304    uplink 0 arp     meter designation
width: 16
field:	15:8	----	0x0 R/W Reserved, must be left ‘0’
field:	7:0	CFIE	0x0 R/W Each bit provides a per-service level enable for using the CFI bit as a policing result indicator.

[LUNE_U2_ARPS]
name: 0x0305    uplink 0 arp     meter designation
width: 16
field:	15:10	----	0x0 R Reserved for future use
field:	9:0	ASVC	0x0 R/W Service Level to “police” ARPs with

pad: 500

[LUNE_U3_CNFG]
name: 0x0400    uplink 0 configuration register
width: 16
field:	15:14	LPRT	0x0 R/W Logical Port Designation, default MUST match physical port. Valid values are {0-3}
field:	13:12	SPEED	0x0 R/W Port speed.
value:		0	1Gb
value:		1	100Mb
value:		2	10Mb
field:	11	TCT	0x0 R/W Transparent Control Frame Tunneling
value:		0	ALL	port supports martini decap of all control frames except pause frames.
value:		1	CTRL	port only allows martini decap of Cisco-WWP control frames
field:	10	-R1-	0x0 R Reserved for future use
field:	9	UTM	0x0 R/W Untagged Mode
value:		0	accept all
value:		1	drop untagged
field:	8	FCE	0x0 R/W Ingress Flow Control Enable
value:		0	Drop	port will drop received 802.3x frames
value:		1	Pass	port will pass received 802.3x frames
field:	7	DRP	0x0 R/W Ingress Transport Drop Mode
value:		0	Pass frames that have unknown Tunnel
value:		1	Drop frames that have unknown Tunnel
field:	6	AM	0x0 R/W ARP Mode
value:		0	police		allow ARP frames to be policed, per police mode
value:		1	do_not_police	do not allow ARP frames to be policed
field:	5	PM	0x0 R/W Police Mode
value:		0	off
value:		1	on
field:	4	FAM	0x0 R/W Frame Accounting Mode
value:		0	Include Minimum IFG in Policing math
value:		1	Do not include Minimum IFG in Policing math
field:	3	EOL	0x0 R/W EOAM loop back enable
value:	0	Disabled
value:	1	Enabled	All frames will be in loopback mode except EOAM PDU
field:	2	DPS	0x0 R/W Disable priority tag stripping
value:		0	Enable	Priority tagged stripping
value:		1	Disable	Priority tagged stripping
field:	1	MR	0x0 R/W ING_COS Mapping MISS Re-Assess Mode
value:		0	do not re-assess  (map) using frame’s .1D priority
value:		1	re-assess (map) using frame’s .1D priority
field:	0	MD	0x0 R/W ING_COS Mapping MISS Drop Mode
value:		0	drop frame
value:		1	port-based default CoS setting


[LUNE_U3_DFLT]
name: 0x0401    uplink 0 default meter designation
width: 16
field:	15:10	----	0x0 R Reserved for future use
field:	9:0	DSVC	0x0 R/W Default Service Level for non-matching frames

[LUNE_U3_DVLN]
name: 0x0402    uplink 0 default vlan
width: 16
field:	15:13	PRI	0x0 R/W D-PRI
field:	12	----	0x0 R/W Reserved for future use
field:	11:0	VID	0x0 R/W D-VID

[LUNE_U3_DTOS]
name: 0x0403    uplink 0 default tos
width: 16
field:	15:7	---	--- R Reserved
field:	6	VLD	0x0 R/W DSCP is valid
value:		0	invalid	yet to be configured
value:		1	valid	can be used for remarking no-match TOS
field:	5:0	DTOS	0x0 R/W Default DSCP/IPP value for “stomping” TOS when mapping is found to be invalid.

[LUNE_U3_CFIE]
name: 0x0404    uplink 0 arp     meter designation
width: 16
field:	15:8	----	0x0 R/W Reserved, must be left ‘0’
field:	7:0	CFIE	0x0 R/W Each bit provides a per-service level enable for using the CFI bit as a policing result indicator.

[LUNE_U3_ARPS]
name: 0x0405    uplink 0 arp     meter designation
width: 16
field:	15:10	----	0x0 R Reserved for future use
field:	9:0	ASVC	0x0 R/W Service Level to “police” ARPs with


