#!/bin/regdecode UIO Driver for Ciena SIRION FPGA #0

# SIRION Register Map and Register Definitions
# Rev 0.14

[SRN_VER]
name: 0x0000    Version register
width: 16
field:	15:8	DSGN	0x51 R Design code specific to Sirion
field:	7:4	MJR	0x0 R Major Version #
field:	3:0	MNR	0x4 R Minor Version #

[SRN_ISR]
name: 0x0001    interrupt status register
width: 16
field:	15:13	HW	0x00 W/C HW-Assist interrupts
field:	12	RTCU	0x00 W/C The real time clock has just been updated.  The rate is determined by the Grand Master Clock Interval
field:	11	RTCR	0x0 W/C The real time clock rolled.  This will occur approximately every 18 hours
field:	10	DRTO	0x0 W/C A 1588 Delay Request was issued and it timed out
field:	9	GMCM	0x0  A 1588 Grand Master Clock Motion was detected. This occurs when a 1588 SYNC packet is received with an SA that is different from the SA specified in register 0x8103
field:	8	CCMF	0x0 W/C CCM Fault Detection.  Software must read the CCM Fault FIFO Table to determine the service that has had the failure
field:	7	-R1-	0x0 W/C As needed
field:	6	-R2-	0x0 W/C As needed
field:	5	-R3-	0x0 W/C As needed
field:	4	-R4-	0x0 W/C As needed
field:	3	-R5-	0x0 W/C As needed
field:	2	GSTAT	0x0 W/C At least one GSTAT Egress statistic's MSB just changed value. SW needs to read all egress statistics to ensure no loss before next rollover
field:	1	EGR_SST	0x0 W/C At least one VSTAT Ingress statistic's MSB just changed value. SW needs to read all egress statistics to ensure no loss before next rollover
field:	0	ING_SST	0x0 W/C At least one VSTAT Egress statistic's MSB just changed value. SW needs to read all egress statistics to ensure no loss before next rollover

[SRN_ISM]
name: 0x0002    interrupt mask register
width: 16
field:	15:13	HW	0x00 W/C HW-Assist interrupts
field:	12	RTCU	0x00 W/C The real time clock has just been updated.  The rate is determined by the Grand Master Clock Interval
field:	11	RTCR	0x0 W/C The real time clock rolled.  This will occur approximately every 18 hours
field:	10	DRTO	0x0 W/C A 1588 Delay Request was issued and it timed out
field:	9	GMCM	0x0  A 1588 Grand Master Clock Motion was detected. This occurs when a 1588 SYNC packet is received with an SA that is different from the SA specified in register 0x8103
field:	8	CCMF	0x0 W/C CCM Fault Detection.  Software must read the CCM Fault FIFO Table to determine the service that has had the failure
field:	7	-R1-	0x0 W/C As needed
field:	6	-R2-	0x0 W/C As needed
field:	5	-R3-	0x0 W/C As needed
field:	4	-R4-	0x0 W/C As needed
field:	3	-R5-	0x0 W/C As needed
field:	2	GSTAT	0x0 W/C At least one GSTAT Egress statistic's MSB just changed value. SW needs to read all egress statistics to ensure no loss before next rollover
field:	1	EGR_SST	0x0 W/C At least one VSTAT Ingress statistic's MSB just changed value. SW needs to read all egress statistics to ensure no loss before next rollover
field:	0	ING_SST	0x0 W/C At least one VSTAT Egress statistic's MSB just changed value. SW needs to read all egress statistics to ensure no loss before next rollover

[SRN_IST]
name: 0x0003    interrupt test register
width: 16
field:	15:13	HW	0x00 W/C HW-Assist interrupts
field:	12	RTCU	0x00 W/C The real time clock has just been updated.  The rate is determined by the Grand Master Clock Interval
field:	11	RTCR	0x0 W/C The real time clock rolled.  This will occur approximately every 18 hours
field:	10	DRTO	0x0 W/C A 1588 Delay Request was issued and it timed out
field:	9	GMCM	0x0  A 1588 Grand Master Clock Motion was detected. This occurs when a 1588 SYNC packet is received with an SA that is different from the SA specified in register 0x8103
field:	8	CCMF	0x0 W/C CCM Fault Detection.  Software must read the CCM Fault FIFO Table to determine the service that has had the failure
field:	7	-R1-	0x0 W/C As needed
field:	6	-R2-	0x0 W/C As needed
field:	5	-R3-	0x0 W/C As needed
field:	4	-R4-	0x0 W/C As needed
field:	3	-R5-	0x0 W/C As needed
field:	2	GSTAT	0x0 W/C At least one GSTAT Egress statistic's MSB just changed value. SW needs to read all egress statistics to ensure no loss before next rollover
field:	1	EGR_SST	0x0 W/C At least one VSTAT Ingress statistic's MSB just changed value. SW needs to read all egress statistics to ensure no loss before next rollover
field:	0	ING_SST	0x0 W/C At least one VSTAT Egress statistic's MSB just changed value. SW needs to read all egress statistics to ensure no loss before next rollover

[SRN_ISB]
name: 0x0004    interrupt test register
width: 16
field:	15:0	BLOCK	0x0 R/W SW writes this register with those bits set that it wishes to hide the interrupt status bit for.

[SRN_IPEN]
name: 0x0005    interface enable register
width: 16
field:	15:10	-R1-	0x0 R Reserved
field:	9	SLP	0x0 R/W Service Loopback Port Processing enable
value:		0	Disabled	All input frame data blocked from FPGA
value:		1	Enabled		Input frame data passed to FPGA
field:	8	SLI	0x0 R/W NNI Port 2 Ingress Interface Enable (box RX path)
value:		0	Disabled	All input frame data blocked from FPGA
value:		1	Enabled		Input frame data passed to FPGA
field:	7:6	-R2-	0x0 R Reserved
field:	5	NTP	0x0 R/W NNI Port Egress Processing Enable (box TX path)
value:		0	Bypass	All frames are passed through unmodified, regardless of other settings.
value:		1	On	Port Configuration settings in effect
field:	4	NTI	0x1 R/W NNI Port Egress Interface Enable (box TX path)
value:		0	Disabled	All input frame data blocked from FPGA
value:		1	Enabled		Input frame data passed to FPGA
field:	3	-R3-	0x0 R Reserved
field:	2	XLB	0x0 R/W XAUI Port Wire Loop back mode
value:		0	Bypass	Normal mode
value:		1	On	Enabled: All XAUI interfaces are placed in serial loop back mode.
field:	1	NRP	0x0 R/W NNI Port Ingress Processing Enable (box RX path)
value:		0	Bypass	Bypass: All frames are passed through unmodified, regardless of other settings.
value:		1	On	Port Configuration settings in effect
field:	0	NRI	0x1 R/W NNI Port Ingress Interface Enable (box RX path)
value:		0	Disabled All input frame data blocked from FPGA
value:		1	Enabled	Input frame data passed to FPGA

pad: 2

[SRN_VETM]
name: 0x0007    VLAN etype mode
width: 16
field:	15:3	-R1-	0x0 R Reserved
field:	2	MD	0x0   Remark all E-types Mode – Port 0 When port’s vlan-ether-type is set to 0x9100, this bit defines how that alternate etype is used:
value:		0	service		Mark only "service" vlans with 0x9100
value:		1	outermost	Mark all outermost VLANs with 0x9100 (including MPLS  transport vlans).
field:	1:0	TYPE	0x0 R/W Service VLAN Etype port 0
value:		0	x8100 Etype
value:		1	x9100 Etype
value:		2	x88A8 Etype
value:		3	Reserved for future use

[SRN_SWAP_ETYP]
name: 0x0008    global internal swap-ethertype for MPLS "transit" traffic
width: 16
field:	15:0	STYPE	0x8850 R/W This Register holds the value used by the hardware to modify the MPLS ETYPE on an ingressing swap frame.  This ETYPE is later used by the hardware to differentiate swap frames from regular MPLS frames at egress.  No frames are sent out of the box with this ETYPE.
value:		0x8850	default

[SRN_EFBT]
name: 0x0009    egress frame buffer threshold register
width: 16
field:	15:12	----	0x0 R Reserved
field:	11:0	UTHR	0x7FF R/W Lower Threshold, point at which an XON request is made, default is half the buffer.

[SRN_PAUS]
name: 0x000A    pause quanta to send when backpressuring local switch
width: 16
field:	15:8	----	0x0 R Reserved
field:	7:0	PAUS	0x0 R/W Pause Quanta sent to VIA when applying backpressure.  This register should be set relative to the upper flow control threshold.

[SRN_OAM_TWP_ERR_EST]
name: 0x000B    OAM TWAMP Error Estimate
width: 16
field:	15:0	EEST	0x0 R/W TWAMP Error Estimate. An estimate of clock and synchronization error. Gets added to all TWAMP reflected frames.

[SRN_OAMC]
name: 0x000C    OAM Control register
width: 16
field:	15:4	TSCNINT	0x32D R/W OAM Timer Scan 3.33ms count control setting  3.33mS /(1024 * clk-period)
value:		0x32D	Lune	(813) clk-period is 4ns
value:		0x28A	Sirion	(650) clk-period is 5ns
field:	3	--	0x0 R Reserved
field:	2	SNM	0x0 R/W OAM Sequence Number Master Select
value:		0	local source for Sequence No. Generator
value:		1	external source for Sequence No. Generator
field:	1	SE	0x0 R/W OAM Profile Table, Sequence Enable
field:	0	TE	0x0 R/W OAM Profile Table, Timer Scan Enable

[SRN_TTL]
name: 0x000D    static TTL used for both Tunnels and VC's
width: 16
field:	15:8	TNL_TTL	0x00 R/W Default TTL value to use with Tunnel Label Stack Entries during MPLS encapsulation
field:	7:0	VC_TTL	0x00 R/W Default TTL value to use with VC Label Stack Entries during MPLS encapsulation

[SRN_DOT1_ETYP]
name: 0x000E    global .1ag ethertype
width: 16
field:	15:0	ETYPE	0x8902 R/W This Register holds the value used by the hardware to identify Y-1731 frames

[SRN_BVID_ETYP]
name: 0x000F    global bvid etype
width: 16
field:	15:0	ETYPE	0x88A8 R/W This Register holds the value used by the hardware to identify PBT B-VIDs

[SRN_ISID_ETYP]
name: 0x0010    global isid etype
width: 16
field:	15:0	ETYPE	0x88E7 R/W This Register holds the value used by the hardware to identify PBT I-SIDs

[SRN_ICFM_ETYP]
name: 0x0011    global ingress CFM etype
width: 16
field:	15:0	ETYPE	0x8902 R/W This Register holds the value used by the hardware to identify PBT CFM frames on ingress (RX)

[SRN_ECFM_ETYP]
name: 0x0012    global egress CFM etype
width: 16
field:	15:0	ETYPE	0x1234 R/W This Register holds the value used by the hardware to identify PBT CFM frames on egress (TX), which in turn need to be converted to the value stored in the register: TLS_BVID_ETYPE.

[SRN_XAUI_DIAG]
name: 0x0013    XAUI diagnostics register
width: 16
field:	15:12	-R1-	0x0 R Reserved
field:	11	SDE	R SLM Disparity Error - 8B/10B disparity error indicator port. Indicates that the XAUI has detected a disparity error
field:	10	SED	R SLM Error Detect - 8B/10B code group violation signal. Indicates that the data has a code violation or a disparity error. Used with disparity error signal to differentiate between a code group error and/or a disparity error. In addition, SED is asserted when the XAUI interface substitutes the received data with 9'b1FE because of XAUI protocol violations
field:	9	SFL	R SLM Frequency Lock - Indicates if the CRU is locked to data mode or locked to the reference clock mode
field:	8	SPL	R SLM Receiver PLL Locked - Indicates if the receiver PLL is phase locked to the CRU reference clock
field:	7	EDE	R EGR Disparity Error - see SLM Disparity Error
field:	6	EED	R EGR Error Detect -  SLM Error Detect
field:	5	EFL	R EGR Frequency Lock - SLM Frequency Lock
field:	4	EPL	R EGR Receiver PLL Locked - SLM Receiver PLL Locked
field:	3	IDE	R IGR Disparity Error - see SLM Disparity Error
field:	2	IED	R IGR Error Detect -  SLM Error Detect
field:	1	IFL	R IGR Frequency Lock - SLM Frequency Lock
field:	0	IPL	R IGR Receiver PLL Locked - SLM Receiver PLL Locked

[SRN_OISR_L1]
name: 0x0014    OAM ISR Level 1
width: 16
field:	15:0	OISR_L1	0x0 R When asserted, each bit in this register indicates that at least one of 16 bits in the associated segment of the 256 bit OAM interrupt status register (OISR_L2) register is asserted. OISR_L1[0] is associated with OISR_L2 segment [15:0]. OISR_L1[15] is associated with OISR_L2 segment [255:240]. Note that any assertion in this register creates a LUNE_ISR register bit assertion.

[SRN_OISR_L2CTL]
name: 0x0015    OAM ISR Level 2 control
width: 16
field:	15:5	-R1-	0x0 R Reserved
field:	4	OISR_L2W	0x0 R/W When asserted, this bit forces a clear of specified bit(s) of the 256 bit OAM interrupt status register (OISR_L2). The cleared bit(s) are defined by OISR_L2ADR and OISR_L2DAT.
field:	3:0	OISR_L2ADR	0x0 R/W This register addresses one of 16 segments in the 256 bit OAM interrupt status register (OISR_L2). Address 0 is associated with OISR_L2[15:0]. Address 15 is associated with OISR_L2 [255:240].

[SRN_OISR_L2CLR]
name: 0x0016    OAM ISR Level 2 Clear
width: 16
field:	15:0	OISR_L2CLR	0x0 R/W When LUNE_OISR_L2CTL is written with OISR_L2W asserted, each asserted bit in this register will force a clear of a corresponding bit in the 256 bit OAM interrupt status register (OISR_L2) segment that OISR__L2ADR defines.

[SRN_OISR_L2DAT]
name: 0x0017    OAM ISR Level 2 data
width: 16
field:	15:0	OISR_L2DAT	0x0 R Contains one of 16 segments in the 256 bit OAM interrupt status register (OISR_L2) as defined by OISR_L2ADR.

[SRN_OAM_DIAG]
name: 0x0018    OAM Sequence Number Diagnostic Register
width: 16
field:	15:8	OAM_SB_TIMEOUT	0x0 R Contains the number of OAM sequence number request timeouts detected on the sideband interface.  When a timeout is detected, the Sirion will complete the frame with a sequence number of 0xDEADBEEF to indicate the occurrence.
field:	7:0	  OAM_SB_LAT	0x0 R The latency of the last sequence number sideband request in terms of clocks.

[SRN_1588_ETYP]
name: 0x0019    global 1588v2 ethertype
width: 16
field:	15:0	ETYPE	0x088F7 R/W This Register holds the value used by the hardware to identify 1588 frames.

pad: 32

[SRN_QDRII]
name: 0x002A    SFP QDRII Register 2
width: 16
field:	15	-R1-	0x0 R Reserved
field:	14	TDON	Training Done
value:		0	Training in progress
value:		1	Done Training
field:	13	TINC	    R The core is nonfunctional. Asserted when the training reaches the maximum number of iterations but fails to adjust the pointersfield:	12:8	LATENCY	0x12 R QDRII read latency from RPS_N to RDY
field:	12	TPNF	    R The core is nonfunctional. The training must find a positive edge on the bit 0 of data. The core did not find this edge
field:	11:7	-R2-	0x0 R Reserved
field:	6	BFAIL	0x0 R Bist Failed
value:		0	Successful BIST
value:		1	Failed BIST , at least one location that did not read back correctly.
field:	5	BIP	0x0 R Bist In Progress
value:		0	complete BIST , QDRII can be enabled
value:		1	running BIST (currently a 2mS duration)
field:	4	BTRG	0x0 W Bist Trigger
field:	3:1	--R3--	0x0 R Reserved
field:	0	DOFN	0x1 R/W DOFFn control register. Direct read/write control of the DOFFn signal driven to the QDRII SRAM. Default is de-asserted (1)

pad: 42

[SRN_RTC_CTRL]
name: 0x0040    realtime clock control register
width: 16
field:	15:3	----	0x0 R/W Reserved
field:	2	EN	0x0 R/W RTC Enable.
value:		0	hold RTC at current value;
value:		1	normal operation.
field:	1	CLR	0x0 R/W On write, this bit is RTC Clear.
value:		1	clear RTC
field:	0	SEL	0x0 R/W RTC Select. Selects between the locally-generated or remote RTC.
value:		0	local
value:		1	remote

[SRN_RTC0]
name: 0x0041    realtime clock register [15:0]
width: 16
field:	15:0	----	0x0 R 1st word of a 64bit NTP RTC clock value.  Reading this register triggers a sampling of the remaining RTC registers.  RTC Word 1, the resulting 32 bit value represents the number of nanoseconds that past since the last second

[SRN_RTC1]
name: 0x0042    realtime clock register [31:16]
width: 16
field:	15:0	----	0x0 R 2nd word of 64bit NTP RTC clock value.  Combined with RTC Word 1, the resulting 32 bit value represents the number of 1/(2^32) fractional seconds that have past since the last second

[SRN_RTC2]
name: 0x0043    realtime clock register [47:32]
width: 16
field:	15:0	----	0x0 R 3rd word of 64bit NTP RTC clock value.  Combined with RTC Word 4, the resulting 32 bit value represents the number of seconds that past since the NTP epoch on 1/1/1900

[SRN_RTC3]
name: 0x0044    realtime clock register [63:48]
width: 16
field:	15:0	----	0x0 R 4th word of 64bit RFC1588 RTC clock value.  Combined with RTC Word 3, the resulting 32 bit value represents the number of seconds that past since the epoch on 1/1/1900

[SRN_RTC_OFST0]
name: 0x0045    realtime clock offset register [15:0]
width: 16
field:	15:0	OFST0	0x0 R/W RTC Offset [15:0].

[SRN_RTC_OFST1]
name: 0x0046    realtime clock offset register [31:16]
width: 16
field:	15:0	OFST1	0x0 R/W RTC Offset [31:16].

[SRN_RTC_OFST2]
name: 0x0047    realtime clock offset register [47:32]
width: 16
field:	15:0	OFST2	0x0 R/W RTC Offset [47:32].

[SRN_RTC_OFST3]
name: 0x0048    realtime clock offset register [63:48]
width: 16
field:	15:0	OFST3	0x0 R/W RTC Offset [63:48].

[SRN_RTC_OFST_CNT0]
name: 0x0049    realtime clock offset count register [15:0]
width: 16
field:	15:0	OCNT0	0x0 R/W RTC Offset Count [15:0]. Lower 16 bits of 20-bit offset count register.

[SRN_RTC_OFST_CNT1]
name: 0x004A    realtime clock offset count register [19:16]
width: 16
field:	15	OSGN	0x0 R/W RTC Offset Sign.
value:		0	Positive	(add offset to current RTC value)
value:		1	Negative	(subtract offset from current RTC value)
field:	14	OGO	0x0 R/W On write, this bit is RTC Offset Go.
value:		1	start offset operation
field:	13:4	----	0x0 R Reserved
field:	3:0	OCNT1	0x0 R/W RTC Offset Count [19:16]. Upper 4 bits of 20-bit offset count register.

[SRN_RTC_DRFT]
name: 0x004B    realtime clock drift adjust register
width: 16
field:	15:10	----	0x0 R Reserved
field:	9	DSGN	0x0 R/W RTC Drift Sign.
value:		0	Positive	(speeds up the RTCrate of count)
value:		1	Negative	(slows down the RTC rate of count).
field:	8:0	DRFT	0x0 R/W RTC Drift Correction. Magnitude of RTC drift correction to apply, in units of 0.296ppm.

[SRN_RTC_1588_0]
name: 0x004C    realtime 1588 clock register [15:0]
width: 16
field:  15:0    ----    0x0     R       1st word of 64bit RFC1588 RTC clock value.  Reading this register triggers a sampling of the remaining RTC registers.  RTC Word 1, the resulting 32 bit value represents the number of nanoseconds that past since the last second

[SRN_RTC_1588_1]
name: 0x004D    realtime 1588 clock register [31:16]
width: 16
field:  15:0    ----    0x0     R       2nd word of 64bit RFC1588 RTC clock value.  Combined with RTC Word 1, the resulting 32 bit value represents the number of nanoseconds that past since the last second.  According to RFC1588, a negative value in this register (bit 15 = 1) means the combined 64 bit value of RTC Word 1 - 4 represents time before the epoch

[SRN_RTC_1588_2]
name: 0x004E    realtime 1588 clock register [47:32]
width: 16
field:  15:0    ----    0x0     R       3rd word of 64bit RFC1588 RTC clock value.  Combined with RTC Word 4, the resulting 32 bit value represents the number of seconds that past since the epoch on 1/1/1970

[SRN_RTC_1588_3]
name: 0x004F    realtime 1588 clock register [63:48]
width: 16
field:  15:0    ----    0x0     R       4th word of 64bit RFC1588 RTC clock value.  Combined with RTC Word 3, the resulting 32 bit value represents the number of seconds that past since the epoch on 1/1/1970

[SRN_RTC_EPO_OFST0]
name: 0x0050    NTP to 1588 Epoch offset register [15:0]
width: 16
field: 15:0     ----    0x0E00  R/W     1st word of a 32bit value indicating the number of seconds between 1/1/1900 and 1/1/1970

[SRN_RTC_EPO_OFST1]
name: 0x0051    NTP to 1588 Epoch offset register [31:16]
width: 16
field: 15:0     ----    0x83AA  R/W     2nd word of a 32bit value indicating the number of seconds between 1/1/1900 and 1/1/1970

pad: 92

[SRN_INDX_SEL]
name: 0x0080    table index select register
width: 16
field:	15	ERR	0x0 R Error occurred during operation, i.e. Write to SRN_INDX register while AIP is set
field:	14	AIP	0x0 R
value:		0	Done	Access complete or no-access in progress (done)
value:		1	inProg	Access in Progress
field:	13	RW	0x0 R/W Read = 1, Write = 0
field:	12:8	----	0x0 R Reserved
field:	7:0	SEL	0x0 R/W Table select (refer to Table 4)

[SRN_INDX0]
name: 0x0081    table index register
width: 16
field:	15:0	ADDR15_0	0x0 R/W Address to access

[SRN_INDX1]
name: 0x0082    table index register
width: 16
field:	15:0	ADDR31_16	0x0 R/W Address to access

[SRN_DAT0]
name: 0x0083    table data 0 register
width: 16

[SRN_DAT1]
name: 0x0084    table data 1 register
width: 16

[SRN_DAT2]
name: 0x0085    table data 2 register
width: 16

[SRN_DAT3]
name: 0x0086    table data 3 register
width: 16

[SRN_DAT4]
name: 0x0087    table data 4 register
width: 16

[SRN_DAT5]
name: 0x0088    table data 5 register
width: 16

[SRN_DAT6]
name: 0x0089    table data 6 register
width: 16

[SRN_DAT7]
name: 0x008A    table data 7 register
width: 16

[SRN_DAT8]
name: 0x008B    table data 8 register
width: 16

pad: 232

[SRN_U0_CNFG]
name: 0x0100    uplink 0 configuration register
width: 16
field:	15:14	LPRT	0x0 R/W Logical Port Designation, default MUST match physical port. Valid values are {0-3}
field:	13:12	-R1-	0x0 R Reserved
field:	11	TCT	0x0 R/W Transparent Control Frame Tunneling
value:		0	ALL	port supports martini decap of all control frames except pause frames.
value:		1	CTRL	port only allows martini decap of Cisco-WWP control frames
field:	10	-R2-	0x0 R Reserved for future use
field:	9	UTM	0x0 R/W Untagged Mode
value:		0	accept all
value:		1	drop untagged
field:	8	FCE	0x0 R/W Ingress Flow Control Enable
value:		0	Drop	port will drop received 802.3x frames
value:		1	Pass	port will pass received 802.3x frames
field:	7	DRP	0x0 R/W Ingress Transport Drop Mode
value:		0	Pass frames that have unknown Tunnel
value:		1	Drop frames that have unknown Tunnel
field:	6	AM	0x0 R/W ARP Mode
value:		0	police		allow ARP frames to be policed, per police mode
value:		1	do_not_police	do not allow ARP frames to be policed
field:	5	PM	0x0 R/W Police Mode
value:		0	off
value:		1	on
field:	4	FAM	0x0 R/W Frame Accounting Mode
value:		0	Include Minimum IFG in Policing math
value:		1	Do not include Minimum IFG in Policing math
field:	3	EOL	0x0 R/W EOAM loop back enable
value:	0	Disabled
value:	1	Enabled	All frames will be in loopback mode except EOAM PDU
field:	2	DPS	0x0 R/W Disable priority tag stripping
value:		0	Enable	Priority tagged stripping
value:		1	Disable	Priority tagged stripping
field:	1	MR	0x0 R/W ING_COS Mapping MISS Re-Assess Mode
value:		0	do not re-assess  (map) using frame’s .1D priority
value:		1	re-assess (map) using frame’s .1D priority
field:	0	MD	0x0 R/W ING_COS Mapping MISS Drop Mode
value:		0	drop frame
value:		1	port-based default CoS setting

[SRN_U0_DFLT]
name: 0x0101    uplink 0 default meter designation
width: 16
field:	15:10	----	0x0 R Reserved for future use
field:	9:0	DSVC	0x0 R/W Default Service Level for non-matching frames

[SRN_U0_DVLN]
name: 0x0102    uplink 0 default vlan
width: 16
field:	15:13	PRI	0x0 R/W D-PRI
field:	12	----	0x0 R/W Reserved for future use
field:	11:0	VID	0x0 R/W D-VID

[SRN_U0_DTOS]
name: 0x0103    uplink 0 default tos
width: 16
field:	15:7	---	--- R Reserved
field:	6	VLD	0x0 R/W DSCP is valid
value:		0	invalid	yet to be configured
value:		1	valid	can be used for remarking no-match TOS
field:	5:0	DTOS	0x0 R/W Default DSCP/IPP value for “stomping” TOS when mapping is found to be invalid.

[SRN_U0_CFIE]
name: 0x0104    uplink 0 arp     meter designation
width: 16
field:	15:8	----	0x0 R/W Reserved, must be left ‘0’
field:	7:0	CFIE	0x0 R/W Each bit provides a per-service level enable for using the CFI bit as a policing result indicator.

[SRN_U0_ARPS]
name: 0x0105    uplink 0 arp     meter designation
width: 16
field:	15:10	----	0x0 R Reserved for future use
field:	9:0	ASVC	0x0 R/W Service Level to “police” ARPs with

pad: 2036

[SRN_SL_CNFG]
name: 0x0500    Service Loopback Port Config
width: 16
field: 15:1     ----    0x0 R Reserved for future use
field: 0        FE      0x0 R/W
value:          0       return all frames sent
value:          1       enable VLAN search results to drop traffic (Normal Mode)

pad: 30

[SRN_SBGR]
name: 0x0510    Sideband general gegister
width: 16
field: 15       CP1             R Clock Present, channel 1 (OAM channel)
value:          0               No clock seen from partner FPGA
value:          1               Clock is being received on SideBand, Channel 1
field: 14       CP0             R Clock Present, channel 0 (Metering channel)
value:          0               No clock seen from partner FPGA
value:          1               Clock is being received on SideBand, Channel 0
field: 13:2     ----    0x0     R Reserved for future use
field: 1        TM1     0x0     R/W TestMode, channel 1 (OAM Channel)
value:          0               Normal Operation
value:          1               Test Mode enabled, see test registers
field: 0        TM0     0x0     R/W TestMode, channel 0 (Metering Channel)
value:          0               Normal Operation
value:          1               Test Mode enabled, see test registers

[SRN_SB_SD0L]
name: 0x0511    Sideband send data channel 0, what to send on low-clock
width: 16
field: 15:12    ----    0x0     R Reserved for future use
field: 11:0     DATA    0x0     R/W DATA to be presented on bus during negedge of clock

[SRN_SB_SD0H]
name: 0x0512    Sideband send data channel 0, what to send on high-clock
width: 16
field: 15:12    ----    0x0     R Reserved for future use
field: 11:0     DATA    0x0     R/W DATA to be presented on bus during posedge of clock

[SRN_SB_SD1L]
name: 0x0513    Sideband send data channel 1, what to send on low-clock
width: 16
field: 15:12    ----    0x0     R Reserved for future use
field: 11:0     DATA    0x0     R/W DATA to be presented on bus during negedge of clock

[SRN_SB_SD1H]
name: 0x0514    Sideband send data channel 1, what to send on high-clock
width: 16
field: 15:12    ----    0x0     R Reserved for future use
field: 11:0     DATA    0x0     R/W DATA to be presented on bus during posedge of clock

[SRN_SB_CD0L]
name: 0x0515    Sideband capture data channel 0, what was captured  on low-clock
width: 16
field: 15:12    ----    0x0     R Reserved for future use
field: 11:0     DATA    0x0     R DATA currently being seen on bus from partner FPGA, on negedge of clock

[SRN_SB_CD0H]
name: 0x0516    Sideband capture data channel 0, what was captured on high-clock
width: 16
field: 15:12    ----    0x0     R Reserved for future use
field: 11:0     DATA    0x0     R DATA currently being seen on bus from partner FPGA, on posedge of clock

[SRN_SB_CD1L]
name: 0x0517    Sideband capture data channel 1, what was captured  on low-clock
width: 16
field: 15:12    ----    0x0     R Reserved for future use
field: 11:0     DATA    0x0     R DATA currently being seen on bus from partner FPGA, on negedge of clock

[SRN_SB_CD1H]
name: 0x0518    Sideband capture data channel 1, what was captured on high-clock
width: 16
field: 15:12    ----    0x0     R Reserved for future use
field: 11:0     DATA    0x0     R DATA currently being seen on bus from partner FPGA, on posedge of clock

