#!/bin/regdecode UIO Driver for Ciena VINMAR FPGA

[VIN_MPU_VERSION]
name: VINMAR fpga Load ID
width: 16
field:	15:8	Major_version	0x0 . Initial release = 1
field:	7:0	Minor_version	0x0 . Initial release = 0

[VIN_MPU_BOARD_ID]
name: CN5150 Board ID
width: 16
field:	15:11	Unused	0x0 . 
field:	10:5	Mezz_board_ID	0x0 . Mezzanine Board ID
field:	4:3	reserved	0x0 . (reserved for future use)
field:	2:0	Main_board_ID	0x0 . Main Board ID

[VIN_MPU_FPGA_RESET]
name: Software-controlled VINMAR Internal Reset
width: 16

[VIN_MPU_STATUS_PWR]
name: Status POWER
width: 16
field:	15:12	Unused	0x0 . 
field:	11	d10ge2_pgood	0x0 . HIGH indicates input pwr voltages are bad
field:	10	d10ge1_pgood	0x0 . HIGH indicates input pwr voltages are bad
field:	9	pwr_in_good[1]	0x0 . HIGH indicates input pwr voltages are bad
field:	8	pwr_in_good[0]	0x0 . HIGH indicates input pwr voltages are bad
field:	7:5	(unused)	0x0 . (unused - was sfp_pwr_good on Alpha)
field:	4	led_pwr_ok	0x0 . HIGH indicates all LED pwr voltages are bad
field:	3	pwr_present[1]	0x0 . HIGH indicates power supply B is not present
field:	2	pwr_present[0]	0x0 . HIGH indicates power supply A is not present
field:	1	pwr_fault_irq[1]	0x0 . HIGH indicates a power supply B fault
field:	0	pwr_fault_irq[0]	0x0 . HIGH indicates a power supply A fault

[VIN_MPU_STATUS_MISC]
name: Status from Miscelaneous sources
width: 16
field:	15:11	Unused	0x0 . 
field:	10	i2c_rtc_irq	0x0 . I2C RTC interrupt (reserved future use)
field:	9:5	board_alarm[4:0]	0x0 . External board alarms (Customer defined)
field:	4	rtc_irq	0x0 . Interrupt from real-time clock
field:	3:2	d10ge2_irq[1:0]	0x0 . Interrupt from Sindar FPGA
field:	1:0	d10ge1_irq[1:0]	0x0 . Interrupt from Sindar FPGA

[VIN_MPU_STATUS_10G]
name: Status 10G Card Presence
width: 16
field:	15:2	Unused	0x0 . 
field:	1:0	d10ge_present[1:0]	0x0 . Set high when 10G board is present.

[VIN_MPU_STATUS_PWR_SEQ]
name: Status POWER Sequencing
width: 16
field:	15:3	Unused	0x0 . 
field:	2	pwr_seq_rst	0x0 . power supervisor device in reset
field:	1	pwr_seq_healthy	0x0 . power supervisor device is healthy
field:	0	pwr_seq_fault	0x0 . power supervisor device in fault

[VIN_MPU_STATUS_CLOCK]
name: Status of Vinmar Clock distribution related signals
width: 16
field:	15:7	Unused	0x0 . 
field:	6	triumph_rclk1_valid	0x0 . Triumph receive clock 1 invalid
field:	5	triumph_rclk0_valid	0x0 . Triumph receive clock 0 invalid
field:	4	zl156_gpio5	0x0 . (Programmable function)
field:	3	zl156_gpio4	0x0 . (Programmable function)
field:	2	zl143_int	0x0 . Interrupt from ZL143 Clock Generator Interrupt
field:	1	zl143_dpll_lock	0x0 . Interrupt from ZL143 Clock Generator PLL lock
field:	0	zl143_dpll_holdover	0x0 . Interrupt from ZL143 Clock Generator PLL holdover

[VIN_MPU_INTR_MASTER_EVNT]
name: Master Interrupt Event Register
width: 16
field:	15:11	Unused	0x0 . 
field:	10	intr_sfp_los_top	0x0 . '1' indicates interrupt event pending from SFP_LOS_TOP register
field:	9	intr_sfp_los_mid	0x0 . '1' indicates interrupt event pending from SFP_LOS_MID register
field:	8	intr_sfp_los_bot	0x0 . '1' indicates interrupt event pending from SFP_LOS_BOT register
field:	7	intr_sfp_los_main	0x0 . '1' indicates interrupt event pending from SFP_LOS_MAIN register
field:	6	intr_status_debug	0x0 . '1' indicates interrupt event pending from DEBUG register
field:	5	intr_status_clock	0x0 . '1' indicates interrupt event pending in INTR_STATUS_CLOCK register
field:	4	intr_status_pwr_seq	0x0 . '1' indicates interrupt event pending in INTR_STATUS_PWR_SEQ register
field:	3	intr_status_10g	0x0 . '1' indicates interrupt event pending in INTR_STATUS_10G register
field:	2	intr_status_i2c	0x0 . '1' indicates interrupt event pending in INTR_STATUS_I2C register
field:	1	intr_status_misc	0x0 . '1' indicates interrupt event pending in INTR_STATUS_MISC register
field:	0	intr_status_pwr	0x0 . '1' indicates interrupt event pending in INTR_STATUS_PWR register

[VIN_MPU_INTR_STATUS_PWR]
name: Interrupt Status POWER
width: 16
field:	15:12	Unused	0x0 . 
field:	11	d10ge2_pgood_evnt	0x0 . HIGH indicates input pwr voltages event
field:	10	d10ge1_pgood_evnt	0x0 . HIGH indicates input pwr voltages event
field:	9	pwr_in_good_evnt[1]	0x0 . HIGH indicates input pwr voltages event
field:	8	pwr_in_good_evnt[0]	0x0 . HIGH indicates input pwr voltages event
field:	7:5	(unused)	0x0 . (unused - was sfp_pwr_good on Alpha)
field:	4	led_pwr_ok_evnt	0x0 . HIGH indicates all LED pwr voltages event
field:	3	pwr_present_evnt[1]	0x0 . HIGH indicates power supply B event
field:	2	pwr_present_evnt[0]	0x0 . HIGH indicates power supply A event
field:	1	pwr_fault_irq_evnt[1]	0x0 . HIGH indicates a power supply B event
field:	0	pwr_fault_irq_evnt[0]	0x0 . HIGH indicates a power supply A event

[VIN_MPU_INTR_STATUS_MISC]
name: Interrupt Status from Miscelaneous sources
width: 16
field:	15:11	Unused	0x0 . 
field:	10	i2c_rtc_irq_evnt	0x0 . I2C RTC interrupt event (reserved future use)
field:	9:5	board_alarm_evnt[4:0]	0x0 . External board alarms event(Customer defined)
field:	4	rtc_irq_evnt	0x0 . Interrupt from real-time clock event
field:	3:2	d10ge2_irq_evnt[1:0]	0x0 . Interrupt from Sindar FPGA event
field:	1:0	d10ge1_irq_evnt[1:0]	0x0 . Interrupt from Sindar FPGA event

[VIN_MPU_INTR_STATUS_I2C]
name: Interrupt Status from I2C
width: 16
field:	15:12	Unused	0x0 . 
field:	11:0	i2c_busext_irq_n[11:0]	0x0 . Active low Interrupts from I2C bus extender.

[VIN_MPU_INTR_STATUS_10G]
name: Interrupt Status from 10G Card Presence
width: 16
field:	15:2	Unused	0x0 . 
field:	1:0	intr_status_10g[1:0]	0x0 . Set high when corresponding bit in STATUS_10G changes from 0->1, or 1->0

[VIN_MPU_INTR_STATUS_PWR_SEQ]
name: Interrupt Status from Power Sequencing
width: 16
field:	15:3	Unused	0x0 . 
field:	2	pwr_seq_rst_evnt	0x0 . power supervisor device reset event
field:	1	pwr_seq_healthy_evnt	0x0 . power supervisor device healthy event
field:	0	pwr_seq_fault_evnt	0x0 . power supervisor device fault event

[VIN_MPU_INTR_STATUS_CLOCK]
name: Interrupt Status from clock distribution
width: 16
field:	15:7	Unused	0x0 . 
field:	6	triumph_rclk1_valid_evnt	0x0 . Triumph receive clock 1 invalid event
field:	5	triumph_rclk0_valid_evnt	0x0 . Triumph receive clock 0 invalid event
field:	4	zl156_gpio5_evnt	0x0 . (Programmable function) event
field:	3	zl156_gpio4_evnt	0x0 . (Programmable function) event
field:	2	zl143_int_evnt	0x0 . Interrupt from ZL143 Clock Generator Interrupt event
field:	1	zl143_dpll_lock_evnt	0x0 . Interrupt from ZL143 Clock Generator PLL lock event
field:	0	zl143_dpll_holdover_evnt	0x0 . Interrupt from ZL143 Clock Generator PLL holdover event

[VIN_MPU_INTR_TEST]
name: Interrupt Status from DEBUG interrupt test enable
width: 16
field:	15:1	Unused	0x0 . 
field:	0	intr_test_evnt	0x0 . Set high when the interrupt test bit in DEBUG[1] changes from 0->1, or 1->0

[VIN_MPU_INTR_MASK_MASTER_EVNT]
name: Interrupt Mask Register 0
width: 16
field:	15:11	Unused	0x0 . 
field:	10	intr_sfp_los_top_mask	0x0 . mask = 1 (interrupt masked OFF)
field:	9	intr_sfp_los_mid_mask	0x0 . mask = 1 (interrupt masked OFF)
field:	8	intr_sfp_los_bot_mask	0x0 . mask = 1 (interrupt masked OFF)
field:	7	intr_sfp_los_main_mask	0x0 . mask = 1 (interrupt masked OFF)
field:	6	intr_status_debug_mask	0x0 . mask = 1 (interrupt masked OFF)
field:	5	intr_status_clock_mask	0x0 . mask = 1 (interrupt masked OFF)
field:	4	intr_status_pwr_seq_mask	0x0 . mask = 1 (interrupt masked OFF)
field:	3	intr_status_10g_mask	0x0 . mask = 1 (interrupt masked OFF)
field:	2	intr_status_i2c_mask	0x0 . mask = 1 (interrupt masked OFF)
field:	1	intr_status_misc_mask	0x0 . mask = 1 (interrupt masked OFF)
field:	0	intr_status_pwr_mask	0x0 . mask = 1 (interrupt masked OFF)

[VIN_MPU_INTR_MASK_PWR]
name: Interrupt Mask Register 1
width: 16
field:	15:12	Unused	0x0 . 
field:	11	d10ge2_pgood_evnt_mask	0x0 . mask = 1 (interrupt masked OFF)
field:	10	d10ge1_pgood_evnt_mask	0x0 . mask = 1 (interrupt masked OFF)
field:	9	pwr_in_good_evnt_mask[1]	0x0 . mask = 1 (interrupt masked OFF)
field:	8	pwr_in_good_evnt_mask[0]	0x0 . mask = 1 (interrupt masked OFF)
field:	7:5	(unused)	0x0 . (unused - was sfp_pwr_good on Alpha)
field:	4	led_pwr_ok_evnt_mask	0x0 . mask = 1 (interrupt masked OFF)
field:	3	pwr_present_evnt_mask[1]	0x0 . mask = 1 (interrupt masked OFF)
field:	2	pwr_present_evnt_mask[0]	0x0 . mask = 1 (interrupt masked OFF)
field:	1	pwr_fault_irq_evnt_mask[1]	0x0 . mask = 1 (interrupt masked OFF)
field:	0	pwr_fault_irq_evnt_mask[0]	0x0 . mask = 1 (interrupt masked OFF)

[VIN_MPU_INTR_MASK_MISC]
name: Interrupt Mask Register 2
width: 16
field:	15:11	Unused	0x0 . 
field:	10	i2c_rtc_irq_evnt_mask	0x0 . mask = 1 (interrupt masked OFF)
field:	9:5	board_alarm_evnt_mask[4:0]	0x0 . mask = 1 (interrupt masked OFF)
field:	4	rtc_irq_evnt_mask	0x0 . mask = 1 (interrupt masked OFF)
field:	3:2	d10ge2_irq_evnt_mask[1:0]	0x0 . mask = 1 (interrupt masked OFF)
field:	1:0	d10ge1_irq_evnt_mask[1:0]	0x0 . mask = 1 (interrupt masked OFF)

[VIN_MPU_INTR_MASK_I2C]
name: Interrupt Mask Register 3
width: 16
field:	15:12	Unused	0x0 . 
field:	11:0	intr_status_i2c_mask[11:0]	0x0 . mask = 1 (interrupt masked OFF)

[VIN_MPU_INTR_MASK_10G]
name: Interrupt Mask Register 4
width: 16
field:	15:2	Unused	0x0 . 
field:	1:0	status_10G_evnt_mask[1:0]	0x0 . mask = 1 (interrupt masked OFF)

[VIN_MPU_INTR_MASK_PWR_SEQ]
name: Interrupt Mask Register 5
width: 16
field:	15:3	Unused	0x0 . 
field:	2	pwr_seq_rst_evnt_mask	0x0 . mask = 1 (interrupt masked OFF)
field:	1	pwr_seq_healthy_evnt_mask	0x0 . mask = 1 (interrupt masked OFF)
field:	0	pwr_seq_fault_evnt_mask	0x0 . mask = 1 (interrupt masked OFF)

[VIN_MPU_INTR_MASK_CLOCK]
name: Interrupt Mask Register 6
width: 16
field:	15:7	Unused	0x0 . 
field:	6	triumph_rclk1_valid_evnt_mask	0x0 . mask = 1 (interrupt masked OFF)
field:	5	triumph_rclk0_valid_evnt_mask	0x0 . mask = 1 (interrupt masked OFF)
field:	4	zl156_gpio5_evnt_mask	0x0 . mask = 1 (interrupt masked OFF)
field:	3	zl156_gpio4_evnt_mask	0x0 . mask = 1 (interrupt masked OFF)
field:	2	zl143_int_evnt_mask	0x0 . mask = 1 (interrupt masked OFF)
field:	1	zl143_dpll_lock_evnt_mask	0x0 . mask = 1 (interrupt masked OFF)
field:	0	zl143_dpll_holdover_evnt_mask	0x0 . mask = 1 (interrupt masked OFF)

[VIN_MPU_INTR_MASK_TEST]
name: Interrupt Mask Register 7
width: 16
field:	15:1	Unused	0x0 . 
field:	0	intr_test_evnt_mask	0x0 . mask = 1 (interrupt masked OFF)

[VIN_MPU_RESET]
name: Reset Register
width: 16
field:	15:7	Unused	0x0 . 
field:	6	zl156_rst	0x0 . '1' = reset to clock management ZL156 device
field:	5	zl143_rst	0x0 . '1' = reset to clock management ZL143 device
field:	4:3	rst_sindar[1:0]	0x0 . '1' = Reset to Sindar FPGAs
field:	2	rst_phy_mgmt	0x0 . '1' = Reset to Management PHY
field:	1	rst_phy_lpbk	0x0 . '1' = Reset to Loopback PHYs
field:	0	rst_pcie	0x0 . '1' = Reset PCie

[VIN_MPU_LED_SHIFT_END]
name: LED_SHIFT_END
width: 16
field:	15:1	Unused	0x0 . 
field:	0	led_shift_end	0x0 . last bit of LED Shift chain

[VIN_MPU_LED_SYS_STATUS]
name: System Status LEDs
width: 16
field:	15:8	Unused	0x0 . 
field:	7	pwr_led2	0x0 . Assertion will illuminate System Power LED 2 red
field:	6	pwr_led1	0x0 . Assertion will illuminate System Power LED 1 red
field:	5	led_sys_alarm_blink_en	0x0 . Assertion will set 1 second blink on System Alarm LED if alarm also selected by [4]
field:	4	led_sys_alarm_yel	0x0 . Assertion will illuminate System Alarm LED yellow
field:	3	led_sys_status_blink_en	0x0 . Assertion will set 1 second blink on System Status LED in colour selected by [2:1].
field:	2	led_sys_status_grn	0x0 . Assertion will illuminate System Status LED green
field:	1	led_sys_status_yel	0x0 . Assertion will illuminate System Status LED yellow
field:	0	led_temp_yellow	0x0 . Assertion will illuminate Temperature LED yellow

[VIN_MPU_FAN_EN]
name: Control register for GASP, FAN_EN
width: 16
field:	15:5	Unused	0x0 . 
field:	4	dying_gasp	0x0 . Logic sets this bit when input pin dying_gasp_irq_n is asserted (low). It can also be written by software.
field:	3:0	fan_enable[3:0]	0x0 . Active high enable for fans 4-1 respectively. They are cleared when a dying gasp interrupt occurs.

[VIN_MPU_FAN_PWM_0]
name: PWM Control register for All Fans
width: 16
field:	15:6	Unused	0x0 . 
field:	5:0	fan_pwm_0[5:0]	0x0 . Pulse Width Modulator Fan speed control. (0x000 = Min Speed. 0x01F = Max Speed.)

[VIN_MPU_FAN_TACH_0]
name: Status register for FAN_TACH 0
width: 16
field:	15:6	Unused	0x0 . 
field:	5:0	fan_tach_0[5:0]	0x0 . Fan speed Indication. (0x000 = Min Speed. 0x00FF = Max Speed.)

[VIN_MPU_FAN_TACH_1]
name: Status register for FAN_TACH 1
width: 16
field:	15:6	Unused	0x0 . 
field:	5:0	fan_tach_1[5:0]	0x0 . Fan speed Indication. (0x000 = Min Speed. 0x00FF = Max Speed.)

[VIN_MPU_FAN_TACH_2]
name: Status register for FAN_TACH 2
width: 16
field:	15:6	Unused	0x0 . 
field:	5:0	fan_tach_2[5:0]	0x0 . Fan speed Indication. (0x000 = Min Speed. 0x00FF = Max Speed.)

[VIN_MPU_FAN_TACH_3]
name: Status register for FAN_TACH 3
width: 16
field:	15:6	Unused	0x0 . 
field:	5:0	fan_tach_3[5:0]	0x0 . Fan speed Indication. (0x000 = Min Speed. 0x00FF = Max Speed.)

[VIN_MPU_I2C_MUX_SEL]
name: Select lines for I2C bus expansion
width: 16
field:	15:6	Unused	0x0 . 
field:	5:0	i2c0_mux_sel[5:0]	0x0 . I2C0 bus mapping:

[VIN_MPU_PWR_SEQ_CTRL]
name: POWER Sequencing Control
width: 16
field:	15:1	Unused	0x0 . 
field:	0	pwr_seq_forced_sd	0x0 . a '1' forces

[VIN_MPU_PWR_SHUTDOWN]
name: Control register for Power Supply Shutdown or Enable
width: 16
field:	15:8	Unused	0x0 . 
field:	7	d10ge2_pwr_enable	0x0 . Active high Power Enable to SFPs. (NOTE: this bit NOT cleared by runtime reset events)
field:	6	d10ge1_pwr_enable	0x0 . Active high Power Enable to SFPs. (NOTE: this bit NOT cleared by runtime reset events)
field:	5:4	(unused)	0x0 . (unused)
field:	3	sfp_pwr_disable	0x0 . Active high Shutdown to SFPs. (Writing '1' drives pin sfp_pwr_disable_n = 0)
field:	2	alarm_pwr_shutoff	0x0 . Active high Shutdown to Alarms. (Writing '1' drives pin alarm_pwr_shutoff_n = 0)
field:	1	pwr2_shutdown	0x0 . Active high Shutdown to Power Supply 2. (Writing '1' drives pin pwr2_shutdown_n = 0)
field:	0	pwr1_shutdown	0x0 . Active high Shutdown to Power Supply 1. (Writing '1' drives pin pwr1_shutdown_n = 0)

[VIN_MPU_TEST_0]
name: Test register
width: 16
field:	15:0	test_reg[15:0]	0x0 . Scratch register for read/write testing of bus access with FPGA

[VIN_MPU_DEBUG]
name: Debug register
width: 16
field:	15:3	Unused	0x0 . 
field:	2	fan_wd_disable	0x0 . 1 = turn off FAN PWM override watchdog
field:	1	intr_test	0x0 . 1 = generate a test interrupt
field:	0	led_test_blink_en	0x0 . 1 = force 10G XFP and mainboard leds to 1 second blink (1G SFP not affected)

[VIN_MPU_SW_RESET]
name: Software-controlled Board Reset
width: 16

[VIN_MPU_RESET_BUTTON]
name: Reset Button monitor
width: 16
field:	15:1	Unused	0x0 . 
field:	0	reset_button	0x0 . Set high when reset button pressed, low otherwise.

[VIN_MPU_TRIUMPH_RESET_CTL]
name: TRIUMPH RESET Control
width: 16
field:	15:1	Unused	0x0 . 
field:	0	triumph_reset_ctl	0x0 . 1 = Triumph Reset will be masked off.

[VIN_MPU_FPGA_INT_SPI_FLASH]
name: FPGA internal SPI Flash access register
width: 16
field:	15:4	Unused	0x0 . 
field:	3	ctrl_flash_odata	0x0 . <read-only> SPI flash read data return
field:	2	ctrl_flash_idata	0x0 . SPI flash write data
field:	1	ctrl_flash_cs_l	0x0 . SPI Flash access select (Active LOW)
field:	0	ctrl_flash_clk	0x0 . SPI Flash clock

[VIN_MPU_FPGA_ICAP_L_ADDR]
name: FPGA reconfiguation image lower offset address register
width: 16
field:	15:0	icap_l_addr[15:0]	0x0 . SPI_Flash address offset to reconfigure from (lower 16bits)

[VIN_MPU_FPGA_ICAP_H_ADDR]
name: FPGA reconfiguation image upper offset address register
width: 16
field:	15:8	Unused	0x0 . 
field:	7:0	icap_h_addr[7:0]	0x0 . SPI_Flash address offset to reconfigure from (upper 8bits)

[VIN_MPU_FPGA_ICAP_CTRL]
name: FPGA Reconfiguation Trigger control
width: 16
field:	15:0	re_config_trigger	0x0 . when set to 0xA5A5, will Trigger FPGA reconfiguation

[VIN_MPU_SFP_LOS_MAIN]
name: SFP LOS signals (main board bank)
width: 16
field:	15:12	Unused	0x0 . 
field:	11:0	sfp_los_main[11:0]	0x0 . SFP (main board bank) LOS

[VIN_MPU_SFP_LOS_BOT]
name: SFP LOS signals (bottom bank)
width: 16
field:	15:12	Unused	0x0 . 
field:	11:0	sfp_los_bot[11:0]	0x0 . SFP (bottom bank) LOS

[VIN_MPU_SFP_LOS_MID]
name: SFP LOS signals (middle bank)
width: 16
field:	15:12	Unused	0x0 . 
field:	11:0	sfp_los_mid[11:0]	0x0 . SFP (middle bank) LOS

[VIN_MPU_SFP_LOS_TOP]
name: SFP LOS signals (top bank)
width: 16
field:	15:12	Unused	0x0 . 
field:	11:0	sfp_los_top[11:0]	0x0 . SFP (top bank) LOS

[VIN_MPU_INTR_SFP_LOS_MAIN]
name: Interrupt Status from SFP_LOS_main interrupt test enable
width: 16
field:	15:12	Unused	0x0 . 
field:	11:0	sfp_los_main_evnt[11:0]	0x0 . Set high when corresponding bit in SFP_LOS_main changes from 0->1, or 1->0

[VIN_MPU_INTR_SFP_LOS_BOT]
name: Interrupt Status from SFP_LOS_BOT interrupt test enable
width: 16
field:	15:12	Unused	0x0 . 
field:	11:0	sfp_los_bot_evnt[11:0]	0x0 . Set high when corresponding bit in SFP_LOS_BOT changes from 0->1, or 1->0

[VIN_MPU_INTR_SFP_LOS_MID]
name: Interrupt Status from SFP_LOS_MID interrupt test enable
width: 16
field:	15:12	Unused	0x0 . 
field:	11:0	sfp_los_mid_evnt[11:0]	0x0 . Set high when corresponding bit in SFP_LOS_MID changes from 0->1, or 1->0

[VIN_MPU_INTR_SFP_LOS_TOP]
name: Interrupt Status from SFP_LOS_TOP interrupt test enable
width: 16
field:	15:12	Unused	0x0 . 
field:	11:0	sfp_los_top_evnt[11:0]	0x0 . Set high when corresponding bit in SFP_LOS_TOP changes from 0->1, or 1->0

[VIN_MPU_INTR_MASK_SFP_LOS_MAIN]
name: Interrupt Mask Register 8
width: 16
field:	15:12	Unused	0x0 . 
field:	11:0	sfp_los_main_evnt_mask[11:0]	0x0 . mask = 1 (interrupt masked OFF)

[VIN_MPU_INTR_MASK_SFP_LOS_BOT]
name: Interrupt Mask Register 9
width: 16
field:	15:12	Unused	0x0 . 
field:	11:0	sfp_los_bot_evnt_mask[11:0]	0x0 . mask = 1 (interrupt masked OFF)

[VIN_MPU_INTR_MASK_SFP_LOS_MID]
name: Interrupt Mask Register 10
width: 16
field:	15:12	Unused	0x0 . 
field:	11:0	sfp_los_mid_evnt_mask[11:0]	0x0 . mask = 1 (interrupt masked OFF)

[VIN_MPU_INTR_MASK_SFP_LOS_TOP]
name: Interrupt Mask Register 11
width: 16
field:	15:12	Unused	0x0 . 
field:	11:0	sfp_los_top_evnt_mask[11:0]	0x0 . mask = 1 (interrupt masked OFF)

[VIN_CFG_RAM0]
offset: 0x100
width: 16

[VIN_CFG_RAM_END]
offset: 0x17e
width: 16

[VIN_CFG_SP_CTRL]
name: Control register for SP_CTRL
width: 16
field:	15:3	Unused	0x0 . 
field:	2	sp_send_buffer	0x0 . Bit indicating that the buffer contents are ready to send to the Sindar.
field:	1:0	sp_config_n[1:0]	0x0 . SP Configure initiate (active low)

[VIN_CFG_SP_VALID_COUNT]
name: Configration RAM Fill Level
width: 16
field:	15:7	Unused	0x0 . 
field:	6:0	sp_valid_count[6:0]	0x0 . Set this register to the number of 16bit words present in the Configuration buffer.

[VIN_CFG_SP_STATUS]
name: Control register for SP_CTRL
width: 16
field:	15:5	Unused	0x0 . 
field:	4	sp_buffer_empty	0x0 . SP data buffer empty indication
field:	3:2	sp_conf_done[1:0]	0x0 . SP Configure Done indication
field:	1:0	sp_status_n[1:0]	0x0 . SP Configure Status indication (1 = FPGA selected by sp_config is not ready, or error during configuration , 0 = FPGA selected by sp_nconfig is ready to be configured)

[VIN_CFG_DISABLE]
name: DISABLE Register
width: 16
field:	15:1	Unused	0x0 . 
field:	0	sp_tri_state	0x0 . Active high tri-state of all sp pins.

pad: 2680

[VIN_SLM_CTRL]
name: Control register for SLM
width: 16
field:	15:1	Unused	0x0 . 
field:	0	slm_ctrl[0]	0x0 . 0 = Normal loopback, 1= Bypass ( No VLAN filtering, No dst/src address swap.)

[VIN_SLM_DCM_CTRL]
name: DCM Control register for SLM
width: 16
field:	15:2	Unused	0x0 . 
field:	1	dcm_ctrl[1]	0x0 . Send Decrement pulse on DCM delay
field:	0	dcm_ctrl[0]	0x0 . Send Increment pulse on DCM delay

[VIN_SLM_STATUS]
name: Status register for SLM
width: 16
field:	15:4	Unused	0x0 . 
field:	3:1	sp_dcm_status	0x0 . DCM Status Byte (see Xilinx Spartan3 User's Guide for details)
field:	0	sp_dcm_lock[0]	0x0 . 1 = RGMII RX CLK DCM is locked.

[VIN_SLM_DEBUG]
name: Debug register
width: 16
field:	15:8	rx_frame_cnt	0x0 . free-running count of frames received(rolls over, not clearable)
field:	7:0	rx_crc_fail_cnt	0x0 . free-running count of Rx CRC errors (rolls over, not clearable)

