--- ./source/private_module/quark/quark_init.c	2021-02-27 07:32:49.866501375 +0000
+++ ./source/private_module/quark/quark_init.c.hotpatch	2021-02-27 07:32:49.866501375 +0000
@@ -43,7 +43,7 @@
 QUARK_COMMON_CONFIG_S g_stQuarkCommonCfgItem;
 EXPORT_SYMBOL(g_stQuarkGlobal);
 EXPORT_SYMBOL(g_stEventCodeMap);
-	
+#define QUARK_PCI_TMO_SUB_RANGE 0xE8
 /*----------------------------------------------*
  * ⲿ˵                                 *
  *----------------------------------------------*/
@@ -51,7 +51,7 @@
 /*----------------------------------------------*
  * ȫֱ                                     *
  *----------------------------------------------*/
-
+OSP_VOID Quark_PatchSetPciTmoSubRange(struct pci_dev *v_pstDev);
 /*----------------------------------------------*
  * ģ鼶                                   *
  *----------------------------------------------*/
@@ -3933,8 +3933,8 @@
         QUARK_TRACE(OSP_DBL_MAJOR, 4522, "Card:%d reset HW(mode:%d) failed!",
         									v_SalCard->ucCardNo,
         									uiResetMode);
-		/*OSж*/
-		Quark_EnableHostIrq(pstLLCard);
+
+
 
         SAS_SPIN_LOCK_IRQSAVE(&v_SalCard->stCardLock, ulFlag);
         v_SalCard->uiFlags &= ~SAL_CARD_RESETTING;
@@ -3960,7 +3960,7 @@
 	*/
 	Quark_EnableHostIrq(pstLLCard);
 	/*END ⵥ:DTS2016032304289 add by chengwei 90006017 2016-03-23*/
-
+    (OSP_VOID)Quark_PatchSetPciTmoSubRange(pstLLCard->stPciInfo.pstPCIDev);
     /*ʼӲ*/
     if (RETURN_OK != Quark_InitHW(pstLLCard))
     {
@@ -12625,4 +12625,67 @@
 	return ;
 }
 
+/*****************************************************************************
+     : Quark_PatchSetPciTmoSubRange
+   оƬλʱPCIE tmoũ
+*****************************************************************************/
+OSP_VOID Quark_PatchSetPciTmoSubRange(struct pci_dev *v_pstDev)
+{
+    OSP_S32 iRet;
+    OSP_U8 ucRegister = 0;
+	SAL_Chip_Phy_Info_S stLLChipInfo;
+
+	SAS_MEMSET(&stLLChipInfo, 0 ,sizeof(SAL_Chip_Phy_Info_S));
+    
+    if (Quark_GetCardNum(v_pstDev, &stLLChipInfo) != RETURN_OK) {
+        QUARK_TRACE(OSP_DBL_MAJOR, 4620, "Get card position failed.");
+        return;
+	}
+	
+	/*жcard no Ч*/
+	QUARK_ASSERT(stLLChipInfo.uiCardId < SAL_MAX_CARD_NUM, return );
+    QUARK_ASSERT(NULL != v_pstDev->bus, return );
+    
+    iRet = SAS_PCI_READ_CONFIG_BYTE(v_pstDev, QUARK_PCI_TMO_SUB_RANGE , &ucRegister);
+    if (iRet != RETURN_OK) {
+        QUARK_TRACE(OSP_DBL_MAJOR, 0x10, "Read device(%x:%x.%x) register 0x%x failed.",
+                    v_pstDev->bus->number,
+                    PCI_SLOT(v_pstDev->devfn),
+                    PCI_FUNC(v_pstDev->devfn),
+                    QUARK_PCI_TMO_SUB_RANGE);
+        return;
+    }
+
+    QUARK_TRACE(OSP_DBL_INFO, 2, "Card:%d device control and status 2 register is:0x%x before set.", 
+                stLLChipInfo.uiCardId,
+                ucRegister);
+    ucRegister |= 0x6;
+    iRet = SAS_PCI_WRITE_CONFIG_BYTE(v_pstDev, QUARK_PCI_TMO_SUB_RANGE , ucRegister);
+    if (iRet != RETURN_OK) {
+        QUARK_TRACE(OSP_DBL_MAJOR, 0x10, "Write device(%x:%x.%x) register 0x%x failed.",
+                    v_pstDev->bus->number,
+                    PCI_SLOT(v_pstDev->devfn),
+                    PCI_FUNC(v_pstDev->devfn),
+                    QUARK_PCI_TMO_SUB_RANGE);
+        return;
+    }
+
+    ucRegister = 0;
+    
+    iRet = SAS_PCI_READ_CONFIG_BYTE(v_pstDev, QUARK_PCI_TMO_SUB_RANGE , &ucRegister);
+    if (iRet != RETURN_OK) {
+        QUARK_TRACE(OSP_DBL_MAJOR, 0x10, "Read device(%x:%x.%x) register 0x%x after set failed.",
+                    v_pstDev->bus->number,
+                    PCI_SLOT(v_pstDev->devfn),
+                    PCI_FUNC(v_pstDev->devfn),
+                    QUARK_PCI_TMO_SUB_RANGE);
+        /* һʧˣӰ칦ܣֻǴӡҲʧ */
+    }
+
+    QUARK_TRACE(OSP_DBL_INFO, 2, "Card:%d device control and status 2 register is:0x%x after set.", 
+                stLLChipInfo.uiCardId,
+                ucRegister);
+    
+    return;  
+}
 
